Patents by Inventor Yung-Feng Cheng

Yung-Feng Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934106
    Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: March 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Yen Liu, Hui-Fang Kuo, Chian-Ting Huang, Wei-Cyuan Lo, Yung-Feng Cheng, Chung-Yi Chiu
  • Publication number: 20240005475
    Abstract: The present invention provides a photomask inspection method, including steps of defining an anchor ratio, providing a photomask and measuring the photomask to obtain a measured ratio, wherein the measured ratio is equal to a value of an image intensity extremum divided by an image intensity threshold or is equal to a value of the image intensity threshold divided by the image intensity extremum when the photomask is measured in an image measurement system tool for a specific critical dimension, and if the measured ratio is larger than the anchor ratio, the photomask is regarded as passing the inspection, and if the measured ratio is smaller than the anchor ratio, the photomask is regarded as failing the inspection.
    Type: Application
    Filed: August 1, 2022
    Publication date: January 4, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Pai-Chi Chen, Chian-Ting Huang, Yung-Feng Cheng
  • Publication number: 20230400759
    Abstract: A photomask design correction method is provided. The photomask design correction method includes the following steps. A layer information data is provided. An OPC process is performed on the layer information data to obtain a first photomask data. A photomask is fabricated based on the first photomask data. A pattern information data of the photomask is obtained after the photomask is fabricated. The difference between the pattern information data and a database of the OPC process is analyzed. An OPC model of the OPC process is corrected based on the difference to obtain a corrected OPC model. The OPC process is performed using the corrected OPC model on the layer information data to obtain a second photomask data.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 14, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Min Cheng Yang, Wei Cyuan Lo, Yung-Feng Cheng
  • Publication number: 20230384689
    Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 30, 2023
    Inventors: Shu-Yen LIU, Hui-Fang KUO, Chian-Ting HUANG, Wei-Cyuan LO, Yung-Feng CHENG, Chung-Yi CHIU
  • Publication number: 20230317779
    Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng, Ming-Jui Chen
  • Publication number: 20230317778
    Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng, Ming-Jui Chen
  • Patent number: 11715759
    Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 1, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng, Ming-Jui Chen
  • Publication number: 20220382169
    Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 1, 2022
    Applicant: United Microelectronics Corp.
    Inventors: Min Cheng Yang, Wei Cyuan Lo, Yung-Feng Cheng
  • Publication number: 20220157933
    Abstract: A method for fabricating minimal fin length includes the steps of first forming a fin-shaped structure extending along a first direction on a substrate, forming a first single-diffusion break (SDB) trench and a second SDB trench extending along a second direction to divide the fin-shaped structure into a first portion, a second portion, and a third portion, and then performing a fin-cut process to remove the first portion and the third portion.
    Type: Application
    Filed: December 11, 2020
    Publication date: May 19, 2022
    Inventors: Chien-Heng Liu, Chia-Wei Huang, Hsin-Jen Yu, Yung-Feng Cheng, Ming-Jui Chen
  • Patent number: 10797059
    Abstract: The present invention provides a method of designing a layout of a static random access memory (SRAM) pattern, the method includes the following steps: firstly, a target pattern is provided, and according to the target pattern, a plurality of first patterns and a first dummy pattern are formed in a substrate, the first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern, and the first dummy pattern is disposed adjacent to the first edge pattern, next, the first dummy pattern is removed, and afterwards, according to the target pattern, a plurality of second patterns are formed in the substrate, the second patterns comprises a second edge pattern that is disposed between the first edge pattern and an original position of the first dummy pattern.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Chang Lin, Wei-Cyuan Lo, Yung-Feng Cheng
  • Publication number: 20200212052
    Abstract: The present invention provides a method of designing a layout of a static random access memory (SRAM) pattern, the method includes the following steps: firstly, a target pattern is provided, and according to the target pattern, a plurality of first patterns and a first dummy pattern are formed in a substrate, the first pattern that disposed at the outermost boundary of the first patterns is defined as a first edge pattern, and the first dummy pattern is disposed adjacent to the first edge pattern, next, the first dummy pattern is removed, and afterwards, according to the target pattern, a plurality of second patterns are formed in the substrate, the second patterns comprises a second edge pattern that is disposed between the first edge pattern and an original position of the first dummy pattern.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 2, 2020
    Inventors: Yu-Chang Lin, Wei-Cyuan Lo, Yung-Feng Cheng
  • Patent number: 10622461
    Abstract: A manufacturing method of a semiconductor device includes the following steps. Trenches are formed on a substrate, and the trenches are formed on a first region and a second region defined on the substrate. A barrier layer is formed conformally in the trenches. A first pull-down process is performed to the barrier layer on the second region. The barrier layer on the first region is covered by a first mask during the first pull-down process. A second pull-down process is performed to the barrier layer on the first region. The barrier layer on the second region is covered by a second mask during the second pull-down process. A proportion of an area of the trenches on the first region to an area of the first region is different from a proportion of an area of the trenches on the second region to an area of the second region.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pai-Chi Chen, Chian-Ting Huang, Yung-Feng Cheng
  • Patent number: 10474026
    Abstract: A method of correcting a layout pattern is provided in the present invention. The method includes the following steps. A layout pattern including at least two adjacent rectangular sub patterns is provided. The layout pattern is then input into a computer system. An optical proximity correction including a bevel correction is then performed. The bevel correction includes forming a bevel at a corner of at least one of the two adjacent rectangular sub patterns, wherein the bevel is formed by chopping the corner, and moving the bevel toward an interaction of two neighboring segments of the bevel if a distance between the bevel and the other rectangular sub pattern is larger than a minimum value. The angle between a surface of the bevel and a surface of the rectangular sub pattern is not rectangular. The layout pattern is output to a mask after the optical proximity correction.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuei-Hsu Chou, Cheng-Te Wang, Yung-Feng Cheng, Jing-Yi Lee
  • Patent number: 10444622
    Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yeh Wu, Chia-Wei Huang, Yung-Feng Cheng
  • Patent number: 10387602
    Abstract: A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: August 20, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yeh Wu, Chia-Wei Huang, Yung-Feng Cheng
  • Publication number: 20190250503
    Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 15, 2019
    Inventors: Tsung-Yeh WU, Chia-Wei HUANG, Yung-Feng CHENG
  • Publication number: 20190228127
    Abstract: A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Inventors: Tsung-Yeh WU, Chia-Wei HUANG, Yung-Feng CHENG
  • Patent number: 10139723
    Abstract: A method of forming a photomask is provided. A first layout pattern is first provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. Thereafter, an optical proximity correction process is performed with reference to both the first layout pattern and the assist feature pattern to the second layout pattern without altering the assist feature pattern to form a third layout pattern by the computer system. Then, the third layout pattern is output to form a photomask.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-I Wei, Chia-Wei Huang, Yung-Feng Cheng
  • Patent number: 10026726
    Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Shih-Fang Tzou, Yi-Wei Chen, Yung-Feng Cheng, Li-Ping Huang, Chun-Hsien Huang, Chia-Wei Huang, Yu-Tse Kuo
  • Publication number: 20180143529
    Abstract: A method of forming a photomask is provided. A first layout pattern is first provided to a computer system and followed by generating an assist feature pattern by the computer system based on the first layout pattern and adding the assist feature pattern into the first layout pattern to form a second layout pattern. Thereafter, an optical proximity correction process is performed with reference to both the first layout pattern and the assist feature pattern to the second layout pattern without altering the assist feature pattern to form a third layout pattern by the computer system. Then, the third layout pattern is output to form a photomask.
    Type: Application
    Filed: November 24, 2016
    Publication date: May 24, 2018
    Inventors: Chih-I Wei, Chia-Wei Huang, Yung-Feng Cheng