Patents by Inventor Yung-Fong Lin
Yung-Fong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955397Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: GrantFiled: November 9, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
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Patent number: 11955522Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer, a source structure, and a drain structure. The buffer layer is disposed on the substrate. The barrier layer is disposed on the buffer layer. The dielectric layer is disposed on the barrier layer. The passivation layer is disposed on the dielectric layer. The source structure and the drain structure are disposed on the passivation layer.Type: GrantFiled: February 13, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Cheng-Wei Chou, Shin-Cheng Lin, Yung-Fong Lin
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Patent number: 11929407Abstract: A method of fabricating a HEMT includes the following steps. A substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon is provided. A passivation layer is formed to cover the group III-V barrier layer and the gate etch stop layer. A gate contact hole and at least one source/drain contact hole are formed in the passivation layer, where the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer. In addition, a conductive layer is conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.Type: GrantFiled: May 30, 2022Date of Patent: March 12, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
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Publication number: 20230058295Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.Type: ApplicationFiled: August 22, 2021Publication date: February 23, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Yang Du, Yung-Fong Lin, Tsung-Hsiang Lin, Yu-Chieh Chou, Cheng-Tao Chou, Yi-Chun Lu, Chun-Hsu Chen
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Patent number: 11552171Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.Type: GrantFiled: October 14, 2021Date of Patent: January 10, 2023Assignee: Vanguard International Semiconductor CorporationInventors: Yung-Fong Lin, Cheng-Tao Chou
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Publication number: 20220336649Abstract: A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.Type: ApplicationFiled: April 15, 2021Publication date: October 20, 2022Inventors: Yung-Fong Lin, Yu-Chieh Chou, Tsung-Hsiang Lin, Li-Wen Chuang
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Publication number: 20220293747Abstract: A method of fabricating a HEMT includes the following steps. A substrate having a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer disposed thereon is provided. A passivation layer is formed to cover the group III-V barrier layer and the gate etch stop layer. A gate contact hole and at least one source/drain contact hole are formed in the passivation layer, where the gate contact hole exposes the gate etch stop layer, and the at least one source/drain contact hole exposes the group III-V channel layer. In addition, a conductive layer is conformally disposed on a top surface of the passivation layer and in the gate contact hole and the at least one source/drain contact hole.Type: ApplicationFiled: May 30, 2022Publication date: September 15, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
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Patent number: 11380767Abstract: A high electron mobility transistor (HEMT) includes a group III-V channel layer, a passivation layer, a group III-V barrier layer, a gate structure, and a source/drain electrode. The passivation layer is disposed on the group III-V channel layer and includes a gate contact hole and a source/drain contact hole, and the group III-V barrier layer is disposed between the group III-V channel layer and the passivation layer. The gate structure includes group III-V gate layer, a gate etch stop layer, and a gate electrode which are stacked in sequence. The gate electrode is disposed in the gate contact hole and conformally covers a portion of the top surface of the passivation layer. The source/drain electrode is disposed in the source/drain contact hole and conformally covers another portion of the top surface of the passivation layer.Type: GrantFiled: April 28, 2020Date of Patent: July 5, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
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Publication number: 20220148938Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: ApplicationFiled: November 9, 2020Publication date: May 12, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Shin-Cheng LIN, Cheng-Wei CHOU, Ting-En HSIEH, Yi-Han HUANG, Kwang-Ming LIN, Yung-Fong LIN, Cheng-Tao CHOU, Chi-Fu LEE, Chia-Lin CHEN, Shu-Wen CHANG
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Publication number: 20220069085Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.Type: ApplicationFiled: October 14, 2021Publication date: March 3, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Yung-Fong LIN, Cheng-Tao CHOU
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Patent number: 11211331Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate and a seed layer on the substrate. The substrate includes a base and a composite layer encapsulating the base. The semiconductor structure also includes an epitaxial layer on the seed layer. The semiconductor structure also includes a semiconductor device on the epitaxial layer, and an interlayer dielectric layer on the epitaxial layer. The interlayer dielectric layer covers the semiconductor device. The semiconductor structure further includes a via structure that penetrates at least the composite layer of the substrate and is in contact with the base.Type: GrantFiled: January 22, 2020Date of Patent: December 28, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Yung-Fong Lin, Li-Wen Chuang, Jui-Hung Yu, Cheng-Tao Chou, Chun-Hsu Chen, Yu-Chieh Chou
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Patent number: 11183563Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.Type: GrantFiled: October 4, 2019Date of Patent: November 23, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Yung-Fong Lin, Cheng-Tao Chou
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Publication number: 20210336016Abstract: A high electron mobility transistor (HEMT) includes a group III-V channel layer, a passivation layer, a group III-V barrier layer, a gate structure, and a source/drain electrode. The passivation layer is disposed on the group III-V channel layer and includes a gate contact hole and a source/drain contact hole, and the group III-V barrier layer is disposed between the group III-V channel layer and the passivation layer. The gate structure includes group III-V gate layer, a gate etch stop layer, and a gate electrode which are stacked in sequence. The gate electrode is disposed in the gate contact hole and conformally covers a portion of the top surface of the passivation layer. The source/drain electrode is disposed in the source/drain contact hole and conformally covers another portion of the top surface of the passivation layer.Type: ApplicationFiled: April 28, 2020Publication date: October 28, 2021Inventors: Ting-En Hsieh, Yu-Chieh Chou, Yung-Fong Lin
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Publication number: 20210257467Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer, a source structure, and a drain structure. The buffer layer is disposed on the substrate. The barrier layer is disposed on the buffer layer. The dielectric layer is disposed on the barrier layer. The passivation layer is disposed on the dielectric layer. The source structure and the drain structure are disposed on the passivation layer.Type: ApplicationFiled: February 13, 2020Publication date: August 19, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Cheng-Wei CHOU, Shin-Cheng LIN, Yung-Fong LIN
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Publication number: 20210225770Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate and a seed layer on the substrate. The substrate includes a base and a composite layer encapsulating the base. The semiconductor structure also includes an epitaxial layer on the seed layer. The semiconductor structure also includes a semiconductor device on the epitaxial layer, and an interlayer dielectric layer on the epitaxial layer. The interlayer dielectric layer covers the semiconductor device. The semiconductor structure further includes a via structure that penetrates at least the composite layer of the substrate and is in contact with the base.Type: ApplicationFiled: January 22, 2020Publication date: July 22, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Yung-Fong LIN, Li-Wen CHUANG, Jui-Hung YU, Cheng-Tao CHOU, Chun-Hsu CHEN, Yu-Chieh CHOU
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Patent number: 11049799Abstract: A semiconductor structure and a method for forming the same are provided. A semiconductor structure includes a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, a first transistor on the epitaxial layer, an interlayer dielectric layer on the epitaxial layer, a dielectric pillar penetrating through the interlayer dielectric layer and the epitaxial layer, and a conductive liner disposed on a sidewall of the dielectric pillar. The conductive liner is electrically connected to the first transistor and the seed layer.Type: GrantFiled: March 19, 2020Date of Patent: June 29, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Yung-Fong Lin, Shin-Cheng Lin, Cheng-Wei Chou, Yu-Chieh Chou
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Patent number: 11011391Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate; forming a silicon layer on the substrate, wherein an edge region of the top surface of the substrate is exposed from the silicon layer; epitaxially growing a GaN-based semiconductor material on the silicon layer and the substrate to form a GaN-based semiconductor layer on the silicon layer and a plurality of GaN-based nodules on the edge region of the top surface of the substrate; and performing a first dry etch step to remove the GaN-based nodules, wherein performing the first dry etch step includes applying a first bias power that is equal to or higher than 1500 W.Type: GrantFiled: July 3, 2019Date of Patent: May 18, 2021Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Yung-Fong Lin, Yu-Chieh Chou
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Publication number: 20210104604Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.Type: ApplicationFiled: October 4, 2019Publication date: April 8, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Yung-Fong LIN, Cheng-Tao CHOU
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Patent number: 10971355Abstract: A substrate includes a ceramic core, a first adhesion layer, a barrier layer, and a second adhesion layer. The first adhesion layer encapsulates the ceramic core and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the first adhesion layer has a first ratio. The barrier layer encapsulates the first adhesion layer and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the barrier layer has a second ratio that is different from the first ratio. The second adhesion layer encapsulates the barrier layer and includes silicon oxynitride, wherein the atomic number ratio of oxygen to nitrogen in silicon oxynitride of the second adhesion layer has a third ratio that is different from the second ratio.Type: GrantFiled: November 21, 2019Date of Patent: April 6, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Kwang-Ming Lin, Yung-Fong Lin
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Publication number: 20210005466Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a substrate; forming a silicon layer on the substrate, wherein an edge region of the top surface of the substrate is exposed from the silicon layer; epitaxially growing a GaN-based semiconductor material on the silicon layer and the substrate to form a GaN-based semiconductor layer on the silicon layer and a plurality of GaN-based nodules on the edge region of the top surface of the substrate; and performing a first dry etch step to remove the GaN-based nodules, wherein performing the first dry etch step includes applying a first bias power that is equal to or higher than 1500 W.Type: ApplicationFiled: July 3, 2019Publication date: January 7, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Yung-Fong LIN, Yu-Chieh CHOU