Patents by Inventor Yung-Fong Lu
Yung-Fong Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9367655Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.Type: GrantFiled: April 10, 2012Date of Patent: June 14, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chang Shih, Chung-min Fu, Ying-Chou Cheng, Yung-Fong Lu, Feng-Yuan Chiu, Chiu Hsiu Chen
-
Patent number: 9141745Abstract: A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells in the cell library is displayed with a respectively different marker indicating a respective fin height. The method further includes generating a second layout for the semiconductor device to be fabricated, by placing or replacing at least one cell from the cell library in a respective location in the first layout. The at least one cell from the cell library comprises a Fin-FET with a respective fin height different from an adjacent Fin-FET in the second layout.Type: GrantFiled: October 31, 2013Date of Patent: September 22, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Min Fu, Yung-Fong Lu, Chung-Hsing Wang
-
Patent number: 9122836Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.Type: GrantFiled: April 14, 2014Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Min Fu, Yung-Fong Lu, Wen-Ju Yang, Chin-Chang Hsu
-
Publication number: 20150121329Abstract: A method includes providing a first layout of a semiconductor device comprising a plurality of cells representing circuit elements, and providing a cell library comprising a plurality of cells in a processor. The circuit elements comprise a plurality of fin field effect transistors (Fin-FETs). Each of the plurality of cells in the cell library is displayed with a respectively different marker indicating a respective fin height. The method further includes generating a second layout for the semiconductor device to be fabricated, by placing or replacing at least one cell from the cell library in a respective location in the first layout. The at least one cell from the cell library comprises a Fin-FET with a respective fin height different from an adjacent Fin-FET in the second layout.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Min FU, Yung-Fong LU, Chung-Hsing WANG
-
Publication number: 20140223391Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.Type: ApplicationFiled: April 14, 2014Publication date: August 7, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Min FU, Yung-Fong LU, Wen-Ju YANG, Chin-Chang HSU
-
Patent number: 8726200Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.Type: GrantFiled: November 23, 2011Date of Patent: May 13, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Min Fu, Yung-Fong Lu, Wen-Ju Yang, Chin-Chang Hsu
-
Patent number: 8677292Abstract: A method of designing an integrated circuit includes providing a standard cell database including a plurality of standard cells; providing an index file having cell-context information indexed to the plurality of standard cells; retrieving the cell-context information of one of the plurality of standard cells from the cell-context file; and applying the index information to a design of the integrated circuit.Type: GrantFiled: February 18, 2010Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Min Fu, Yen-Pin Chen, Yung-Fong Lu
-
Publication number: 20130267047Abstract: The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model.Type: ApplicationFiled: April 10, 2012Publication date: October 10, 2013Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: I-Chang Shih, Chung-min Fu, Ying-Chou Cheng, Yung-Fong Lu, Feng-Yuan Chiu, Chiu Hsiu Chen
-
Publication number: 20130132913Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.Type: ApplicationFiled: November 23, 2011Publication date: May 23, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Min FU, Yung-Fong LU, Wen-Ju YANG, Chin-Chang HSU
-
Publication number: 20100275167Abstract: A method of designing an integrated circuit includes providing a standard cell database including a plurality of standard cells; providing an index file having cell-context information indexed to the plurality of standard cells; retrieving the cell-context information of one of the plurality of standard cells from the cell-context file; and applying the index information to a design of the integrated circuit.Type: ApplicationFiled: February 18, 2010Publication date: October 28, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Min Fu, Yen-Pin Chen, Yung-Fong Lu