Patents by Inventor Yung-Fung Lin

Yung-Fung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of fabricating semiconductor structures with two-step etching
    Patent number: 11682713
    Abstract: A method of fabricating a semiconductor structure includes forming a GaN-based semiconductor layer on a substrate, forming a silicon-containing insulating layer on the GaN-based semiconductor layer, forming a recess in the silicon-containing insulating layer in a first etching step, wherein the first etching step is performed by using a fluorine-containing etchant and applying a first bias power, and enlarging the recess to extend into the GaN-based semiconductor layer in a second etching step, wherein the second etching step is performed by using the same fluorine-containing etchant as the first etching step and applying a second bias power that is greater than the first bias power. In addition, a method of fabricating a high electron mobility transistor is provided.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: June 20, 2023
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yung-Fung Lin, Yu-Chieh Chou
  • METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES WITH TWO-STEP ETCHING
    Publication number: 20210367061
    Abstract: A method of fabricating a semiconductor structure includes forming a GaN-based semiconductor layer on a substrate, forming a silicon-containing insulating layer on the GaN-based semiconductor layer, forming a recess in the silicon-containing insulating layer in a first etching step, wherein the first etching step is performed by using a fluorine-containing etchant and applying a first bias power, and enlarging the recess to extend into the GaN-based semiconductor layer in a second etching step, wherein the second etching step is performed by using the same fluorine-containing etchant as the first etching step and applying a second bias power that is greater than the first bias power. In addition, a method of fabricating a high electron mobility transistor is provided.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 25, 2021
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yung-Fung LIN, Yu-Chieh CHOU
  • Methods of fabricating semiconductor structures and high electron mobility transistors
    Patent number: 11121229
    Abstract: A method of fabricating a semiconductor structure includes forming a GaN-based semiconductor layer on a substrate, forming a silicon-containing insulating layer on the GaN-based semiconductor layer, forming a recess in the silicon-containing insulating layer in a first etching step, wherein the first etching step is performed by using a fluorine-containing etchant and applying a first bias power, and enlarging the recess to extend into the GaN-based semiconductor layer in a second etching step, wherein the second etching step is performed by using the same fluorine-containing etchant as the first etching step and applying a second bias power that is greater than the first bias power. In addition, a method of fabricating a high electron mobility transistor is provided.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 14, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yung-Fung Lin, Yu-Chieh Chou
  • Semiconductor structure and high electron mobility transistor with a substrate having a pit, and methods for fabricating semiconductor structure
    Patent number: 10453947
    Abstract: A semiconductor device includes a substrate, a flowable dielectric material and a GaN-based semiconductor layer. The substrate has a pit exposed from an upper surface of the substrate, the flowable dielectric material fully fills the pit, and the GaN-based semiconductor layer is disposed over the substrate and the flowable dielectric material.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: October 22, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yung-Fung Lin, Cheng-Wei Chou, Szu-Yao Chang, Cheng-Tao Chou, Hsiu-Ming Chen
  • METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND HIGH ELECTRON MOBILITY TRANSISTORS
    Publication number: 20190207012
    Abstract: A method of fabricating a semiconductor structure includes forming a GaN-based semiconductor layer on a substrate, forming a silicon-containing insulating layer on the GaN-based semiconductor layer, forming a recess in the silicon-containing insulating layer in a first etching step, wherein the first etching step is performed by using a fluorine-containing etchant and applying a first bias power, and enlarging the recess to extend into the GaN-based semiconductor layer in a second etching step, wherein the second etching step is performed by using the same fluorine-containing etchant as the first etching step and applying a second bias power that is greater than the first bias power. In addition, a method of fabricating a high electron mobility transistor is provided.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yung-Fung Lin, Yu-Chieh Chou