Patents by Inventor Yung-Han Chiu
Yung-Han Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11917837Abstract: A method of forming the semiconductor device is provided. The method includes following steps. A memory structure is formed over a first conductive line over a substrate and is electrically connected to the first conductive line. A sacrificial layer is formed on the memory structure. A spacer layer is formed to cover the memory structure and the sacrificial layer. A first dielectric layer is formed to cover the spacer layer. A planarization process is performed to remove a portion of the first dielectric layer. A second dielectric layer is formed on the spacer layer and the first dielectric layer. A patterning process is performed to form an opening exposing a portion of the top surface of the sacrificial layer. The sacrificial layer is removed to form a recess. A second conductive line is formed in the opening and the recess to be electrically coupled to the memory structure.Type: GrantFiled: August 29, 2022Date of Patent: February 27, 2024Assignee: Winbond Electronics Corp.Inventors: Yung-Han Chiu, Shu-Ming Li, Po-Yen Hsu
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Publication number: 20230309297Abstract: A semiconductor structure includes an active region of a substrate, a gate electrode layer disposed over the active region, an isolation structure surrounding the active region and the gate electrode layer, and a gate dielectric layer. The gate dielectric layer includes a first portion interposed between the bottom surface of the gate electrode layer and the top surface of the active region. The gate dielectric layer also includes a second portion interposed between the isolation structure and the sidewall of the active region.Type: ApplicationFiled: March 21, 2023Publication date: September 28, 2023Inventors: Yung-Han CHIU, Shu-Ming LI
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Publication number: 20230268417Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.Type: ApplicationFiled: April 20, 2023Publication date: August 24, 2023Inventors: Shu-Ming LEE, Yung-Han CHIU, Chia-Hung LIU, Tzu-Ming OU YANG
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Patent number: 11664438Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.Type: GrantFiled: November 5, 2019Date of Patent: May 30, 2023Assignee: WINBOND ELECTRONICS CORP.Inventors: Shu-Ming Lee, Yung-Han Chiu, Chia-Hung Liu, Tzu-Ming Ou Yang
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Publication number: 20220406846Abstract: A method of forming the semiconductor device is provided. The method includes following steps. A memory structure is formed over a first conductive line over a substrate and is electrically connected to the first conductive line. A sacrificial layer is formed on the memory structure. A spacer layer is formed to cover the memory structure and the sacrificial layer. A first dielectric layer is formed to cover the spacer layer. A planarization process is performed to remove a portion of the first dielectric layer. A second dielectric layer is formed on the spacer layer and the first dielectric layer. A patterning process is performed to form an opening exposing a portion of the top surface of the sacrificial layer. The sacrificial layer is removed to form a recess. A second conductive line is formed in the opening and the recess to be electrically coupled to the memory structure.Type: ApplicationFiled: August 29, 2022Publication date: December 22, 2022Applicant: Winbond Electronics Corp.Inventors: Yung-Han Chiu, Shu-Ming Li, Po-Yen Hsu
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Patent number: 11476305Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a first conductive line over a substrate and a memory structure over the first conductive line. The memory structure is electrically coupled to the first conductive line through a conductive via. A spacer layer is laterally aside the memory structure and covers sidewalls of the memory structure. A first dielectric layer is on the spacer layer and laterally aside the memory structure. A second dielectric layer is on the memory structure, the spacer layer and the first dielectric layer. A second conductive line penetrates through the second dielectric layer, the first dielectric layer and the spacer layer to electrically couple to the memory structure. The second conductive line includes a body part at least partially embedded in the second dielectric layer and an extension part underlying the body part and laterally protruding from a sidewall of the body part.Type: GrantFiled: February 3, 2021Date of Patent: October 18, 2022Assignee: Winbond Electronics Corp.Inventors: Yung-Han Chiu, Shu-Ming Li, Po-Yen Hsu
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Publication number: 20220246680Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a first conductive line over a substrate and a memory structure over the first conductive line. The memory structure is electrically coupled to the first conductive line through a conductive via. A spacer layer is laterally aside the memory structure and covers sidewalls of the memory structure. A first dielectric layer is on the spacer layer and laterally aside the memory structure. A second dielectric layer is on the memory structure, the spacer layer and the first dielectric layer. A second conductive line penetrates through the second dielectric layer, the first dielectric layer and the spacer layer to electrically couple to the memory structure. The second conductive line includes a body part at least partially embedded in the second dielectric layer and an extension part underlying the body part and laterally protruding from a sidewall of the body part.Type: ApplicationFiled: February 3, 2021Publication date: August 4, 2022Applicant: Winbond Electronics Corp.Inventors: Yung-Han Chiu, Shu-Ming Li, Po-Yen Hsu
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Publication number: 20210134980Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.Type: ApplicationFiled: November 5, 2019Publication date: May 6, 2021Inventors: Shu-Ming LEE, Yung-Han CHIU, Chia-Hung LIU, Tzu-Ming OU YANG
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Patent number: 7648910Abstract: A method of manufacturing an opening is described. First, a substrate including a conductive portion and a dielectric layer both formed thereon is provided. The conductive portion at least includes a conductive layer and a passivation layer from bottom-up, and the dielectric layer covers the conductive portion. A first dry etching step is then performed to form an opening on the passivation layer by using a reactive gas containing a high polymer gas. The bottom of the opening has an initial dimension, and an obtuse angle is included by the bottom of the opening and an inner sidewall of the opening. Next, an opening enlarging step is performed to reach a target dimension of the bottom of the opening. The target dimension is larger than the initial dimension and to the least extent the conductive layer is not exposed by the opening.Type: GrantFiled: May 15, 2007Date of Patent: January 19, 2010Assignee: Winbond Electronics Corp.Inventors: Ching-Jen Han, Wen-Shun Lo, Yung-Han Chiu
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Publication number: 20080160756Abstract: A method of manufacturing an opening is described. First, a substrate including a conductive portion and a dielectric layer both formed thereon is provided. The conductive portion at least includes a conductive layer and a passivation layer from bottom-up, and the dielectric layer covers the conductive portion. A first dry etching step is then performed to form an opening on the passivation layer by using a reactive gas containing a high polymer gas. The bottom of the opening has an initial dimension, and an obtuse angle is included by the bottom of the opening and an inner sidewall of the opening. Next, an opening enlarging step is performed to reach a target dimension of the bottom of the opening. The target dimension is larger than the initial dimension and to the least extent the conductive layer is not exposed by the opening.Type: ApplicationFiled: May 15, 2007Publication date: July 3, 2008Applicant: WINBOND ELECTRONICS CORP.Inventors: Ching-Jen Han, Wen-Shun Lo, Yung-Han Chiu