Patents by Inventor Yung-Hao Lu
Yung-Hao Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240194593Abstract: A method of forming a semiconductor device includes the following operations. A substrate is provided with an electric component. A composite dielectric layer is formed on the substrate and covers the electric component. An opening is formed through the composite dielectric layer. A directional etching process is performed to widen an upper portion of the opening. A metal feature is formed in the opening.Type: ApplicationFiled: February 10, 2023Publication date: June 13, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Wei Su, Yung-Hsu Wu, Hsin-Ping Chen, Chih Wei LU, Wei-Hao Liao, Hsi-Wen Tien, Cherng-Shiaw Tsai
-
Publication number: 20240194765Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.Type: ApplicationFiled: January 29, 2024Publication date: June 13, 2024Inventors: Yoh-Rong Liu, Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Li-Chi Yu, Sen-Hong Syue
-
Patent number: 12009407Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.Type: GrantFiled: April 20, 2023Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Kai Lin, Yung-Cheng Lu, Che-Hao Chang, Chi On Chui
-
Publication number: 20240179900Abstract: A non-volatile memory cell includes a tunneling part; a coupling transistor, including a coupling gate part, a first conductive region and a second conductive region, wherein the coupling gate part is coupled to the tunneling part and disposed in the first conductive region; a read transistor with a read gate part coupled to the tunneling part for forming an electron tunneling ejection path in an erase mode, and forming an electron tunneling injection path in a program mode; and a select transistor, connected in series with the read transistor, for forming a read path with the read transistor in a read mode.Type: ApplicationFiled: December 22, 2022Publication date: May 30, 2024Applicant: AMIC Technology CorporationInventors: Hsiao-Hua Lu, Yung-Tien Peng, Chun-Hao Huang
-
Publication number: 20240162333Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.Type: ApplicationFiled: January 24, 2024Publication date: May 16, 2024Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
-
Publication number: 20240142833Abstract: An electronic device includes a substrate, a driving element, a first insulating layer, a pixel electrode layer, and a common electrode layer. The driving element is disposed on the substrate. The first insulating layer is disposed on the driving element. The pixel electrode layer is disposed on the first insulating layer. The first insulating layer comprises a hole, and the pixel electrode layer is electrically connected to the driving element through the hole. The common electrode layer is disposed on the pixel electrode layer. The common electrode layer comprises a slit, and the slit has an edge, and the edge is disposed in the hole.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Applicant: Innolux CorporationInventors: Wei-Yen Chiu, Ming-Jou Tai, You-Cheng Lu, Yi-Shiuan Cherng, Yi-Hsiu Wu, Chia-Hao Tsai, Yung-Hsun Wu
-
Publication number: 20240136428Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
-
Publication number: 20240120272Abstract: Embodiments of the present disclosure relates to a method for forming a semiconductor device structure. The method includes including forming one or more conductive features in a first interlayer dielectric (ILD), forming an etch stop layer on the first ILD, forming a second ILD over the etch stop layer, forming one or more openings through the second ILD and the etch stop layer to expose a top surface of the one or more first conductive features, wherein the one or more openings are formed by a first etch process in a first process chamber, exposing the one or more openings to a second etch process in a second process chamber so that the shape of the or more openings is elongated, and filling the one or more openings with a conductive material.Type: ApplicationFiled: January 15, 2023Publication date: April 11, 2024Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih Wei LU, Yung-Hsu WU, Cherng-Shiaw TSAI, Chia-Wei SU
-
Patent number: 11942329Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor protruding structure over a substrate and surrounding the semiconductor protruding structure with an insulating layer. The method also includes forming a dielectric layer over the insulating layer. The method further includes partially removing the dielectric layer and insulating layer using a planarization process. As a result, topmost surfaces of the semiconductor protruding structure, the insulating layer, and the dielectric layer are substantially level with each other. In addition, the method includes forming a protective layer to cover the topmost surfaces of the dielectric layer. The method includes recessing the insulating layer after the protective layer is formed such that the semiconductor protruding structure and a portion of the dielectric layer protrude from a top surface of a remaining portion of the insulating layer.Type: GrantFiled: March 3, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yi Kao, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
-
Patent number: 11923432Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.Type: GrantFiled: January 3, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yoh-Rong Liu, Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Li-Chi Yu, Sen-Hong Syue
-
Publication number: 20240071330Abstract: A display device includes a display panel. The display panel has a functional display area. The functional display area includes a plurality of display pixels and a plurality of light transmitting regions. The plurality of display pixels are around by the plurality of the light transmitting regions. A boundary between one of the plurality of display pixels and one of the plurality of light transmitting regions comprises an arc segment.Type: ApplicationFiled: November 3, 2023Publication date: February 29, 2024Applicant: Innolux CorporationInventors: Chia-Hao Tsai, Ming-Jou Tai, Yi-Shiuan Cherng, Yu-Shih Tsou, You-Cheng Lu, Yung-Hsun Wu
-
Patent number: 11916132Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.Type: GrantFiled: June 30, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
-
Patent number: 7375943Abstract: A tri-phase surge protector comprises a first zinc oxide ceramic body; a first electrode layer on a surface of the first zinc oxide ceramic body and having a first electrode, and the first electrode includes a first terminal; a second electrode layer on another surface of the first zinc oxide ceramic body; a second zinc oxide ceramic body on the second electrode layer; a third electrode layer on another surface of the second zinc oxide ceramic body and having a second electrode, and the second electrode includes a second terminal; a third zinc oxide ceramic body on the second electrode layer and at the second zinc oxide ceramic body; and a fourth electrode layer on another surface of the third zinc oxide ceramic body and having a third electrode, and the third electrode includes a third terminal. The invention also discloses a method for manufacturing a tri-phase surge protector.Type: GrantFiled: November 22, 2005Date of Patent: May 20, 2008Inventor: Yung-Hao Lu
-
Publication number: 20070217110Abstract: A tri-phase surge protector comprises a first zinc oxide ceramic body; a first electrode layer on a surface of the first zinc oxide ceramic body and having a first electrode, and the first electrode includes a first terminal; a second electrode layer on another surface of the first zinc oxide ceramic body; a second zinc oxide ceramic body on the second electrode layer; a third electrode layer on another surface of the second zinc oxide ceramic body and having a second electrode, and the second electrode includes a second terminal; a third zinc oxide ceramic body on the second electrode layer and at the second zinc oxide ceramic body; and a fourth electrode layer on another surface of the third zinc oxide ceramic body and having a third electrode, and the third electrode includes a third terminal. The invention also discloses a method for manufacturing a tri-phase surge protector.Type: ApplicationFiled: November 22, 2005Publication date: September 20, 2007Inventor: Yung-Hao Lu