Abstract: Embodiments of mechanisms for processing a wafer are provided. A method for processing a wafer includes placing the wafer into a processing assembly and heating the wafer. The method also includes producing an exhaust flow from the processing assembly via a fluid-conduit assembly. The method further includes detecting an exhaust pressure of the exhaust flow in the fluid-conduit assembly and producing a first signal and a second signal corresponding to the exhaust pressure. In addition, the method includes regulating the exhaust flow in response to the first signal and controlling the processing assembly in response to the second signal.

Abstract: Embodiments of mechanisms for processing a wafer are provided. A method for processing a wafer includes placing the wafer into a processing assembly and heating the wafer. The method also includes producing an exhaust flow from the processing assembly via a fluid-conduit assembly. The method further includes detecting an exhaust pressure of the exhaust flow in the fluid-conduit assembly and producing a first signal and a second signal corresponding to the exhaust pressure. In addition, the method includes regulating the exhaust flow in response to the first signal and controlling the processing assembly in response to the second signal.

Abstract: A mask pattern having an anti-ESD ring which protects the pattern region of the mask from damage due to ESD events. The anti-ESD ring has a space between two broad border regions formed of an opaque metal such as chrome. ESD fingers, or rods extend from one of the border regions to within a small gap of the other border region. These ESD fingers act as lightning rods so that ESD events preferably occur across this small gap between the ESD fingers and one of the border regions. The ESD fingers are small enough so that any metal transferred across the gap in an ESD event is very small. The gap is located so that any metal transferred is far away from the pattern region of the mask. The ESD fingers confine ESD events to a preferred region of the mask and damage to the pattern region is avoided.

Abstract: An electrostatic discharge-free container equipped with a metal shield for holding an insulating article therein is described. In the container, an electrically conductive layer substantially covers a bottom lid made of a non-conductive material so as to sufficiently shield the insulating article from electrostatic discharge damages. The present invention novel ESD-free container may further be provided with a metal knob situated in a top lid of the container, or be provided with a metal enclosure positioned inside the container between the top lid and the insulating article. The metal layer that substantially overlaps the bottom lid may be injection molded as an insert in the bottom lid, or may be coated or plated on the bottom lid. The present invention novel ESD-free container eliminates any electrostatic discharge from occurring on a reticle plate and thus avoiding any potential damages.

Abstract: A method for forming a polycide/oxide/polysilicon capacitor on a silicon wafer with improved dielectric stability and reliability is described wherein an in-situ high temperature anneal is applied to the wafer within a CVD reactor immediately prior to the deposition of the silicon oxide capacitor dielectric layer. The in-situ anneal causes sufficient fluorine outgassing of the polycide layer to prevent fluorine degradation of the subsequently deposited oxide capacitor dielectric. The capacitance of the completed capacitor is increased by as much as 10% when compared to a comparable not in-situ anneal conducted prior to the insertion of the wafer into the CVD reactor.

Abstract: A chemical vapor deposition (CVD) method for forming with enhanced sheet resistance uniformity tungsten silicide layers upon substrates. There is formed upon a first substrate within a chemical vapor deposition (CVD) reactor chamber a first tungsten silicide layer through a chemical vapor deposition (CVD) method. The first substrate is then removed from the chemical vapor deposition (CVD) reactor chamber. The chemical vapor deposition (CVD) reactor chamber is then cleaned with a fluorine containing plasma and subsequently purged with a mixture of silane and an inert gas. There may then be formed with enhanced sheet resistance uniformity upon a second substrate within the chemical vapor deposition (CVD) reactor chamber a second tungsten silicide layer through the chemical vapor deposition (CVD) method.

Abstract: A method for backside grinding a semiconductor wafer and forming a contamination free bonding pad connection. The method comprises forming a passivation layer over a metal layer. Applying a photoresist pattern with an opening which will define a bonding pad area and removing the passivation layer exposed in the opening. Next, the photoresist is removed, but a polymer residue is often formed on the surfaces of the passivation layer surrounding the bonding pad. In a novel step, the residue is removed using an etchant containing Dimethylsulfoxide (D.M.D.O.) aud Monoethanolamine (M.E.A.) and is followed by au oxygen plasma treatment. Next, the device side of the wafer is covered with a protective tape and the backside of the wafer is grouud back. The tape is removed revealing a contamination free bonding pad area. A bonding connection is then made to the bonding pad.

Abstract: An apparatus for applying spin-on-glass material to a wafer under controlled humidity conditions is described, The apparatus comprises a treatment chamber. Within the treatment chamber are a spin-on-glass coater spin table, a plurality of hotplates connected to one another and from the coater spin table by a moving belt, and wafer handlers to transfer wafers onto the coater spin table and onto the moving belt. A dehumidifier is disposed on top of the treatment chamber and a humidity control unit is disposed on top of the dehumidifier through which air is drawn and whereby relative humidity within the treatment chamber can be controlled.

Abstract: A method is described for fabricating an integrated circuit with polycide gate electrodes in which there is no delamination of the overlying dielectric layer. A polysilicon layer over a gate dielectric is provided on a silicon substrate. A silicide layer is formed over the polysilicon layer using WF.sub.6 and SiH.sub.4 as the reaction gases. The silicide and polysilicon layers are patterned to form polycide gate electrodes. The substrate is annealed initially in an inert gas atmosphere to remove excess fluorine gas, then in an oxygen atmosphere. Lightly doped source and drain ion implants are performed. Spacers are formed on the sidewalls of the polycide gate electrodes. Source/drain ion implants are performed with include fluoride ions. The substrate is degassed in an inert atmosphere to remove the excess fluoride ions. A dielectric layer is deposited over the pattern of polycide gate electrodes and flowed. There is no excess fluorine gas concentration to form a bubble in the dielectric layer.

Abstract: A new method of planarizing an integrated circuit is described. A first coating of a silicate spin-on-glass material is applied to the surface of a patterned conductor layer to be planarized. The spin-on-glass material is applied under low relative humidity, filling the valleys of the irregular structure of the conductor layer. The first spin-on-glass layer is covered with a second coating of the spin-on-glass material also applied under low relative humidity. Then, both first and second spin-on-glass layers are cured. This method provides a uniform spin-on-glass dielectric layer upon which a second conductor layer may now be successfully applied.

Abstract: A method for forming multiple layer metallurgy, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion, that is the positive charge between the first via layer and the SOG is described. A semiconductor substrate having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least partially within semiconductor substrate electrically separating certain of these source/drain regions from one another are provided. A passivation layer is formed over the surfaces of said patterns.