Abstract: A pixel circuit includes a driving transistor, a storage capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor. A first end of the driving transistor is electrically coupled to a system high voltage terminal. The driving transistor is configured to control a driving current supplied to a light emitting element. A first end of the storage capacitor is electrically coupled to a control end of the driving transistor. A first end of the first transistor is electrically coupled to a second end of the storage capacitor, and a second end of the first transistor is configured to receive a data signal. When the first transistor is turned on according to the first control signal, the storage capacitor resets a voltage at the control end of the driving transistor, by a capacitive coupling effect, according to a change in voltage of the data signal.

Abstract: A display device includes a pixel circuit and a stage of a scan driver. The stage of the scan driver is electrically coupled to the pixel circuit. The stage of the scan driver is configured to output a first scan signal and a second scan signal to the pixel circuit. A first enable voltage of the first scan signal is at a first logic level, and a first disable voltage of the first scan signal is at a second logic level. A second enable voltage of the second scan signal is at the second logic level.

Abstract: A pixel circuit includes a driving transistor, a storage capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor. A first end of the driving transistor is electrically coupled to a system high voltage terminal. The driving transistor is configured to control a driving current supplied to a light emitting element. A first end of the storage capacitor is electrically coupled to a control end of the driving transistor. A first end of the first transistor is electrically coupled to a second end of the storage capacitor, and a second end of the first transistor is configured to receive a data signal. When the first transistor is turned on according to the first control signal, the storage capacitor resets a voltage at the control end of the driving transistor, by a capacitive coupling effect, according to a change in voltage of the data signal.

Abstract: Disclosed are a display panel and a pixel circuit thereof. The pixel circuit includes a driving transistor, a data write-in circuit, a compensation circuit, a voltage control circuit, a light-emitting switch, and a light-emitting element. The driving transistor receives a power supply voltage. The data write-in circuit receives a first scanning signal, an emission signal, and a write-in data signal, stores the write-in data signal, and provides the write-in data signal to a control end of the driving transistor. The compensation circuit has a first switch and a second switch coupled to a relay end and controlled by a second scanning signal. The voltage control circuit adjusts a voltage difference between the control end of the driving transistor and the relay end. The light-emitting switch is coupled between a second end of the driving transistor and the light-emitting element, and is controlled by the emission signal.

Abstract: The present disclosure provides a semiconductor device, including a buffer layer, a first sub-chip and a second sub-chip, and a connecting element. The first sub-chip and the second sub-chip are separately arranged on the buffer layer. Each of the first sub-chip and the second sub-chip includes a first diffusion layer, an active layer, and a second diffusion layer. The first diffusion layer, the active layer, and the second diffusion layer are sequentially arranged on the buffer layer in a top-down approach. The first diffusion layer and the buffer layer are first-type epitaxial layers, and the second diffusion layer is a second-type epitaxial layer. The connecting element is configured to couple the second diffusion layer of the first sub-chip and the first diffusion layer of the second sub-chip.

Abstract: A display panel including a substrate, multiple display pixels, an encapsulation structure, and an auxiliary layer is provided. The substrate includes a display region, a bendable region, and a buffer region positioned therebetween. The display pixels are disposed in the display region. The encapsulation structure is overlapped with the display region and covers the display pixels. The auxiliary layer is overlapped with the bendable region and has a top surface. A first height is included between a top surface of the auxiliary layer and a surface of the substrate. The auxiliary layer and the encapsulation structure define a recess overlapped with the buffer region. A second height is included between a bottom surface of the recess positioned in the buffer region and the surface of the substrate. A difference between the first height and the second height is greater than 0 ?m and less than or equal to 4 ?m.

Abstract: A display panel including a substrate, a plurality of bonding pads, and a plurality of conductive traces is provided. The substrate has a substrate edge, a display region, and a peripheral region disposed between the substrate edge and the display region. The plurality of bonding pads are arranged in the peripheral region of the substrate. The plurality of conductive traces are electrically connected to the bonding pads. The conductive traces extend between the bonding pads and the substrate edge and have a plurality of breaks. A method of fabricating the display panel is also provided.

Abstract: A device substrate includes a first substrate, a second substrate, a plurality of first bonding pads, a plurality of second bonding pads, a plurality of first leads, and a plurality of second leads. The first and second bonding pads are separated from each other. The first bonding pads are arranged in a first column. The second bonding pads are arranged in a second column. The first and second leads respectively overlap the first and second bonding pads. The first lead includes a first extension portion and a first branch portion. The first extension portion extends from the first column to the second column. The first branch portion is connected to an end of the first extension portion close to the second column. An angle is present between the first extension portion and the first branch portion.

Abstract: A display panel including a substrate, multiple display pixels, an encapsulation structure, and an auxiliary layer is provided. The substrate includes a display region, a bendable region, and a buffer region positioned therebetween. The display pixels are disposed in the display region. The encapsulation structure is overlapped with the display region and covers the display pixels. The auxiliary layer is overlapped with the bendable region and has a top surface. A first height is included between a top surface of the auxiliary layer and a surface of the substrate. The auxiliary layer and the encapsulation structure define a recess overlapped with the buffer region. A second height is included between a bottom surface of the recess positioned in the buffer region and the surface of the substrate. A difference between the first height and the second height is greater than 0 ?m and less than or equal to 4 ?m.

Abstract: A display panel including a substrate, a plurality of bonding pads, and a plurality of conductive traces is provided. The substrate has a substrate edge, a display region, and a peripheral region disposed between the substrate edge and the display region. The plurality of bonding pads are arranged in the peripheral region of the substrate. The plurality of conductive traces are electrically connected to the bonding pads. The conductive traces extend between the bonding pads and the substrate edge and have a plurality of breaks. A method of fabricating the display panel is also provided.

Abstract: A display panel is provided. The display panel includes a substrate, a pixel array, a peripheral circuit, and a protective layer. The substrate includes a display region and a non-display region. The pixel array is located in the display region of the substrate. The peripheral circuit is located in the non-display region. The protective layer is located in the display region and the non-display region. The peripheral circuit and the pixel array are covered by the protective layer. The protective layer in the non-display region has a plurality of openings, which expose the substrate. The apertures of the openings is between 1 ?m and 1 mm, and the spacing between the openings is 10 ?m and 1 cm.

Abstract: A display panel is provided. The display panel includes a substrate, a pixel array, a peripheral circuit, and a protective layer. The substrate includes a display region and a non-display region. The pixel array is located in the display region of the substrate. The peripheral circuit is located in the non-display region. The protective layer is located in the display region and the non-display region. The peripheral circuit and the pixel array are covered by the protective layer. The protective layer in the non-display region has a plurality of openings, which expose the substrate. The apertures of the openings is between 1 ?m and 1 mm, and the spacing between the openings is 10 ?m and 1 cm.

Abstract: A display panel is provided. The display panel includes a substrate, a pixel array, a peripheral circuit, and a protective layer. The substrate includes a display region and a non-display region. The pixel array is located in the display region of the substrate. The peripheral circuit is located in the non-display region. The protective layer is located in the display region and the non-display region. The peripheral circuit and the pixel array are covered by the protective layer. The protective layer in the non-display region has a plurality of openings, which expose the substrate. The apertures of the openings is between 1 ?m and 1 mm, and the spacing between the openings is 10 ?m and 1 cm.

Abstract: An electrophoretic display system includes an electrophoretic display panel, a timing controller, a data driver, and a gate driver. The data driver includes a first serial-to-parallel converter and a data converter. The first serial-to-parallel converter receives a plurality of first series data and converts the first series data into a plurality of second series data. The quantity of the second series data is more than the quantity of the first series data. The data converter receives the second series data and is electrically connected to the electrophoretic display panel. Besides, the data converter converts the second series data into display voltages, and the quantity of the display voltages is more than the quantity of the second series data. The gate driver is electrically connected to the electrophoretic display panel and the timing controller and controlled by the timing controller to provide gate driving voltages to the electrophoretic display panel.

Abstract: A display panel is provided. The display panel includes a substrate, a pixel array, a peripheral circuit, and a protective layer. The substrate includes a display region and a non-display region. The pixel array is located in the display region of the substrate. The peripheral circuit is located in the non-display region. The protective layer is located in the display region and the non-display region. The peripheral circuit and the pixel array are covered by the protective layer. The protective layer in the non-display region has a plurality of openings, which expose the substrate. The apertures of the openings is between 1 ?m and 1 mm, and the spacing between the openings is 10 ?m and 1 cm.

Abstract: An electrophoretic display system includes an electrophoretic display panel, a timing controller, a data driver, and a gate driver. The data driver includes a first serial-to-parallel converter and a data converter. The first serial-to-parallel converter receives a plurality of first series data and converts the first series data into a plurality of second series data. The quantity of the second series data is more than the quantity of the first series data. The data converter receives the second series data and is electrically connected to the electrophoretic display panel. Besides, the data converter converts the second series data into display voltages, and the quantity of the display voltages is more than the quantity of the second series data. The gate driver is electrically connected to the electrophoretic display panel and the timing controller and controlled by the timing controller to provide gate driving voltages to the electrophoretic display panel.