Patents by Inventor Yung-Hsien Chang

Yung-Hsien Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10514417
    Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Zeng Kang, Chih-Hsien Chang, Wen-Shen Chou, Yung-Chow Peng
  • Publication number: 20190381348
    Abstract: A magnetron mechanism of an unpowered treadmill contains: a driving body, a one-way transmission element, and a magnetron mechanism. The driving body includes a frame, a connection fence, a front wheel assembly, and a connection shaft. The one-way transmission element is mounted on the connection fence of the frame. The magnetron mechanism is fixed on the connection fence and includes a rotary shaft, a drive wheel, a driven wheel, a belt, a flywheel, a resistance element, and an adjustment unit. The resistance element has a pair of fixing sheets and multiple magnetic parts. Each of the multiple magnetic parts has a rotatable connection portion. The adjustment unit has a steel cable, an end of which is connected with the resistance element so that the steel cable pulls the resistance element to swing along the rotatable connection portion.
    Type: Application
    Filed: June 4, 2019
    Publication date: December 19, 2019
    Inventors: Tsung-Hsien Tsai, Yung-I Chang
  • Patent number: 10445008
    Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: October 15, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yung-Chun Li, Ping-Hsien Lin, Yu-Ming Chang
  • Patent number: 10418002
    Abstract: Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 17, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ping Chao, Ting-An Lin, Tung-Hsing Wu, Kung-Tsun Yang, Wan-Yu Chen, Chuang-Chi Chiou, Ping-yao Wang, Wei-Gen Wu, Hsin-Hao Chung, Chih-Ming Wang, Han-Liang Chou, Chung Hsien Lee, Yung-Chang Chang, Chi-Cheng Ju
  • Publication number: 20190195943
    Abstract: An IC degradation sensor is disclosed. The IC degradation management sensor includes an odd number of first logic gates electrically connected in a ring oscillator configuration, each first logic gate having an input and an output. Each first logic gate further includes a first PMOS transistor, a first NMOS transistor and a second logic gate having an input and an output. The input of the second logic gate is the input of the first logic gate, and the drains of the first PMOS transistor and the first NMOS transistor are electrically connected to the output of the second logic gate, and the output of the second logic gate is the output of the first logic gate.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Zeng KANG, Chih-Hsien CHANG, Wen-Shen CHOU, Yung-Chow PENG
  • Patent number: 10096407
    Abstract: A surface mountable over-current protection device comprises a PTC material layer, first and second conductive layers, left and right electrodes, left and right conductive members, and left and right insulating members. The PTC material layer comprises a left notch at a left end and a right notch at a right end. The first conductive layer comprises a primary portion disposed on an upper surface of the PTC material layer and a secondary portion extending over the left notch, and the second conductive layer comprises a primary portion disposed on a lower surface of the PTC material layer and a secondary portion extending over the underside of the right notch. The left conductive member connects to the left electrode and the first conductive layer and isolates from the second conductive layer. The right conductive member connects to the right electrode and the second conductive layer and isolates from the first conductive layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 9, 2018
    Assignee: POLYTRONICS TECHNOLOGY CORP.
    Inventors: Chun Teng Tseng, Wen Feng Lee, Yung Hsien Chang, Yao Te Chang
  • Patent number: 9997906
    Abstract: An over-current protection device comprises first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer has a resistivity less than 0.05 ?·cm and comprises a polymer matrix, a conductive ceramic filler and a carbon-containing conductive filler. The polymer matrix comprises a fluoropolymer having a melting point higher than 150° C. and comprises 50-60% by volume of the PTC material layer. The conductive ceramic filler having a resistivity less than 500??·cm is dispersed in the polymer matrix and comprises 40-45% by volume of the PTC material layer. The carbon-containing conductive filler is dispersed in the polymer matrix and comprises 0.5-5% by volume of the PTC material layer. At 25° C., a ratio of a hold current to an area of the over-current protection device is 0.21-0.3 A/mm2, and a ratio of an endurable power to the area of the over-current protection device is 4.8-7.2 W/mm2.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 12, 2018
    Assignee: Polytronics Technology Corp.
    Inventors: Hsiu Che Yen, Yung Hsien Chang, Zhen Yu Dong, Yao Te Chang, David Shau Chew Wang
  • Publication number: 20180033527
    Abstract: A surface mountable over-current protection device comprises a PTC material layer, first and second conductive layers, left and right electrodes, left and right conductive members, and left and right insulating members. The PTC material layer comprises a left notch at a left end and a right notch at a right end. The first conductive layer comprises a primary portion disposed on an upper surface of the PTC material layer and a secondary portion extending over the left notch, and the second conductive layer comprises a primary portion disposed on a lower surface of the PTC material layer and a secondary portion extending over the underside of the right notch. The left conductive member connects to the left electrode and the first conductive layer and isolates from the second conductive layer. The right conductive member connects to the right electrode and the second conductive layer and isolates from the first conductive layer.
    Type: Application
    Filed: February 21, 2017
    Publication date: February 1, 2018
    Inventors: Chun Teng TSENG, Wen Feng LEE, Yung Hsien CHANG, Yao Te CHANG
  • Publication number: 20080168076
    Abstract: A digital audio ripping device is proposed, which is designed for use to convert the digital audio data that are stored in a particular format on a storage medium, such as Audio CD files, into a standard computer multimedia format, such as the MP3 format, such that the user can utilize a portable MP3 player for playback of MP3-formatted digital audio files extracted from Audio CD. The proposed digital audio ripping device is characterized by the capability of Audio CD ripping to an MP3 multimedia player without having to use a PC, and the capability of performing a folder reorganizing procedure in the event of the MP3 multimedia player being downloading and installing an iTunes program via the Internet so as to allow the MP3 multimedia player to use the iTunes program for playback of the digital audio files extracted from the Audio CD.
    Type: Application
    Filed: January 8, 2007
    Publication date: July 10, 2008
    Applicant: INVENTEC MULTIMEDIA & TELECOM CORPORATION
    Inventors: Yung-Hsien Chang, Lun-Chuan Chang
  • Patent number: 7079592
    Abstract: The present invention relates to both of a bi-stage correlation calculation demodulation system, and a fast walsh block demodulation device at a receiver, wherein the bi-stage correlation calculation demodulation system has a characteristic of bi-stage correlation calculation in which the subsequent second-stage correlation calculations are dependent on the first-stage correlation calculation results by utilizing an incomplete orthogonal property within CCK codewords to arrange the CCK codewords operated in the first-stage correlation calculations and second-stage correlation calculations properly and respectively.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: July 18, 2006
    Assignee: Accton Technology Corporation
    Inventors: Cheng-Yuan Chang, Jie-Hau Huang, Hong-Chin Lin, Guu-Chang Yang, Yung-Hsien Chang, Hsuan-Ching Chao
  • Publication number: 20030147478
    Abstract: A complementary code keying (CCK) demodulation system is disclosed, and more particularly relates to both of a bi-stage correlation calculation demodulation system, and a fast walsh block demodulation device at a receiver, wherein the bi-stage correlation calculation demodulation system has a characteristic of bi-stage correlation calculation in which the subsequent second-stage correlation calculations are dependent on the first-stage correlation calculation results by utilizing an incomplete orthogonal property within CCK codewords to arrange the CCK codewords operated in the first-stage correlation calculations and second-stage correlation calculations properly and respectively. Thus, the operation quantities of correlation calculations are reduced substantially, and the codeword transmitted from transmitter is resolved rapidly, so that the complexity of receiver is decreased and the demodulating speed is speeded up.
    Type: Application
    Filed: June 14, 2002
    Publication date: August 7, 2003
    Applicant: Accton Technology Corporation
    Inventors: Cheng-Yuan Chang, Jie-Hau Huang, Hong-Chin Lin, Guu-Chang Yang, Yung-Hsien Chang, Hsuan-Ching Chao
  • Patent number: 6223143
    Abstract: A quantitative risk assessment system (QRAS) builds a risk model of a system for which risk of failure is being assessed, then analyzes the risk of the system corresponding to the risk model. The QRAS performs sensitivity analysis of the risk model by altering fundamental components and quantifications built into the risk model, then re-analyzes the risk of the system using the modifications. More particularly, the risk model is built by building a hierarchy, creating a mission timeline, quantifying failure modes, and building/editing event sequence diagrams. Multiplicities, dependencies, and redundancies of the system are included in the risk model. For analysis runs, a fixed baseline is first constructed and stored. This baseline contains the lowest level scenarios, preserved in event tree structure. The analysis runs, at any level of the hierarchy and below, access this baseline for risk quantitative computation as well as ranking of particular risks.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: April 24, 2001
    Assignee: The United States Government as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Robert M Weinstock, Carol S Smidts, Ali Mosleh, Yung-Hsien Chang, Sankaran Swaminathan, Francisco J Groen, Zhibin Tan