Patents by Inventor Yung-Hsien Wu
Yung-Hsien Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240099994Abstract: Provided are sustained-release pharmaceutical compositions including a ketamine pamoate salt and a pharmaceutically acceptable carrier thereof. The compositions include aqueous suspension, solution and matrix delivery system, which can provide sustained release for anesthesia, analgesia or treatment of central nervous system and anti-inflammatory diseases.Type: ApplicationFiled: December 18, 2020Publication date: March 28, 2024Applicant: ALAR PHARMACEUTICALS INC.Inventors: Tong-Ho Lin, Yung-Shun Wen, Chai-Hsien Chen, Ying-Ting Liu, Rui-Zhi Hou, Zhi-Rong Wu
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Publication number: 20240077649Abstract: An optical lens structure includes an optical substrate, a predetermined processing area, an optical micro thin film and a micro thin film pattern. The optical substrate has a first surface and a second surface and rays of light passes through the optical substrate. The predetermined processing area is provided on the first surface or the second surface of the optical substrate. The micro thin optical film is formed on the predetermined processing area of the first surface or the second surface by non-contact processing with an ink liquid spot material via nozzles. The micro thin film pattern is formed from the micro thin optical film to thereby provide an optical characteristic.Type: ApplicationFiled: October 18, 2022Publication date: March 7, 2024Inventors: TIEN-SHU WU, YEN-TING WU, YUNG-HSIEN LU
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Publication number: 20240071656Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.Type: ApplicationFiled: January 13, 2023Publication date: February 29, 2024Inventors: Chien Hui WU, Yung-Hsien CHANG, Cheng-Yu TUNG, Ming-Hsun LU, Yi-An SHA
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Patent number: 10930583Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.Type: GrantFiled: July 27, 2018Date of Patent: February 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen
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Patent number: 10319675Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.Type: GrantFiled: January 13, 2016Date of Patent: June 11, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen
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Patent number: 10163516Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a charge trapping structure, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the charge trapping structure. The charge trapping structure is between the first insulating layer and the second insulating layer. The gate electrode is over the second insulating layer. The charge trapping structure includes a first layer and a second layer. The first layer includes zinc oxide, tin dioxide, titanium oxide, zinc tin oxide, indium oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxynitride, tin oxynitride, titanium oxynitride, zinc tin oxynitride, indium oxynitride, indium zinc oxynitride, or indium gallium zinc oxynitride.Type: GrantFiled: June 5, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Chen Huang, Kuang-Hsin Chen, Yung-Hsien Wu, Wen-Chao Shen
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Publication number: 20180337123Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.Type: ApplicationFiled: July 27, 2018Publication date: November 22, 2018Inventors: Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen
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Publication number: 20180337248Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.Type: ApplicationFiled: July 31, 2018Publication date: November 22, 2018Inventors: I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen
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Patent number: 10068984Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.Type: GrantFiled: September 1, 2016Date of Patent: September 4, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen
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Patent number: 10008494Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.Type: GrantFiled: January 11, 2017Date of Patent: June 26, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen
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Publication number: 20170330976Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a charge trapping structure, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the charge trapping structure. The charge trapping structure is between the first insulating layer and the second insulating layer. The gate electrode is over the second insulating layer. The charge trapping structure includes a first layer and a second layer. The first layer includes zinc oxide, tin dioxide, titanium oxide, zinc tin oxide, indium oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxynitride, tin oxynitride, titanium oxynitride, zinc tin oxynitride, indium oxynitride, indium zinc oxynitride, or indium gallium zinc oxynitride.Type: ApplicationFiled: June 5, 2017Publication date: November 16, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Chen HUANG, Kuang-Hsin CHEN, Yung-Hsien WU, Wen-Chao SHEN
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Publication number: 20170317182Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.Type: ApplicationFiled: September 1, 2016Publication date: November 2, 2017Inventors: I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen
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Publication number: 20170200673Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes an interconnection structure formed on a semiconductor substrate; and a capacitor disposed in the interconnection structure. The interconnection structure includes a top electrode; a bottom electrode; a dielectric material layer sandwiched between the top and bottom electrodes; and a nanocrystal layer embedded in the dielectric material layer.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Inventors: Cheng-Chieh Lai, Meng-Ting Yu, Yung-Hsien Wu, Kuang-Hsin Chen
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Patent number: 9673340Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a first layer, a second layer, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the first layer. The second layer is between the first layer and the second insulating layer. The gate electrode is over the second insulating layer. There is a P-N junction between the first layer and the second layer. The semiconductor device structure includes a first doped region and a second doped region in the semiconductor substrate. The first layer, the first doped region, and the second doped region have a first type conductivity, which is opposite to a second type conductivity of the second layer.Type: GrantFiled: May 13, 2016Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: I-Chen Huang, Kuang-Hsin Chen, Yung-Hsien Wu, Wen-Chao Shen
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Publication number: 20170125417Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.Type: ApplicationFiled: January 11, 2017Publication date: May 4, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh LAI, Kuang-Hsin CHEN, Shih-Kai FAN, Yung-Hsien WU, Yu-Hsun CHEN
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Patent number: 9570568Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.Type: GrantFiled: May 28, 2015Date of Patent: February 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Chieh Lai, Kuang-Hsin Chen, Shih-Kai Fan, Yung-Hsien Wu, Yu-Hsun Chen
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Publication number: 20160351673Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.Type: ApplicationFiled: May 28, 2015Publication date: December 1, 2016Inventors: Cheng-Chieh LAI, Kuang-Hsin CHEN, Shih-Kai FAN, Yung-Hsien WU, Yu-Hsun CHEN
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Publication number: 20140220771Abstract: A process of manufacturing a Write-Once-Read-Many-times memory, at least includes the following steps: (A) providing a substrate as a lower electrode; (B) depositing a first oxide layer on the substrate; (C) depositing at least one or more silicon/germanium (Si/Ge) layers on the first oxide layer; (D) depositing a second oxide layer on the at least one or more Si/Ge layers; (E) carrying out a rapid thermal annealing to form SiGe nanocrystals embedded in the first dioxide layer and the second oxide layer; and (F) depositing a conductive layer on the second oxide layer as an upper electrode. The SiGe nanocrystals embedded in the Al2O3 bilayer as the active layer of the WORM memory offers high thermal stability, so that low operating voltage, fast writing, ideal reading durability, persistence at high temperature, and the highly reliable memory performance for effectively reading data at high temperature can be achieved.Type: ApplicationFiled: February 5, 2013Publication date: August 7, 2014Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Yung-Hsien Wu, Min-Lin Wu
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Patent number: 8288193Abstract: The present disclosure uses ammonia plasma for nitrification and for further forming a barrier pattern on a substrate. Then, a selective emitter is fabricated by forming light doping and heavy doping at one time through diffusion into the substrate. Therein, a plurality of trenches for obtaining a front contact is formed at the same time on forming the barrier pattern. Thus, the fabrication process is simplified and the cost is reduced for fabricating a selective emitter solar cell.Type: GrantFiled: February 16, 2010Date of Patent: October 16, 2012Assignee: National Tsing Hua UniversityInventors: Yung-Hsien Wu, Li-Karn Wang, Feng-Der Chin