Abstract: A pipeline module circuit structure with reduced power consumption and a method for operating the pipeline module circuit structure are provided. The pipeline module circuit structure comprises a plurality of pipeline stages and a clock generator, each of the pipeline stages connected to adjacent pipeline stages through a bus. A clock controller is installed in each of the pipeline stages, so as to set the clock frequency of a preceding pipeline stage to an idle frequency or stop when a present pipeline stage starts to operate and to set the clock frequency of a next pipeline stage to an operation frequency when the present pipeline stage is about to cease, such that the power consumption of the pipeline module circuit structure is effectively reduced.

Abstract: An inquiring apparatus and method thereof is provided for assisting the CPU to inquire the state of the peripheral device. When the CPU needs to perform an inquiring process to wait for a peripheral device to come to an expected state, an inquiring apparatus is activated, instead of the CPU, to perform an inquiring process. The CPU is placed in a power-saving state which stops outputting the clock to the CPU when the inquiring apparatus performs the inquiring process. The inquiring process includes outputting a read cycle to the peripheral device receiving a current state of the peripheral device in response to the read cycle; and comparing the current state with the expected state. If the current state and the expected state are the same, the clock is outputted to the CPU again.

Abstract: A pipeline module circuit structure with reduced power consumption and a method for operating the pipeline module circuit structure are provided. The pipeline module circuit structure comprises a plurality of pipeline stages and a clock generator, each of the pipeline stages connected to adjacent pipeline stages through a bus. A clock controller is installed in each of the pipeline stages, so as to set the clock frequency of a preceding pipeline stage to an idle frequency or stop when a present pipeline stage starts to operate and to set the clock frequency of a next pipeline stage to an operation frequency when the present pipeline stage is about to cease, such that the power consumption of the pipeline module circuit structure is effectively reduced.

Abstract: A pipeline module circuit structure with reduced power consumption and a method for operating the pipeline module circuit structure are provided. The pipeline module circuit structure comprises a plurality of pipeline stages and a clock generator, each of the pipeline stages connected to adjacent pipeline stages through a bus. A clock controller is installed in each of the pipeline stages, so as to set the clock frequency of a preceding pipeline stage to an idle frequency or stop when a present pipeline stage starts to operate and to set the clock frequency of a next pipeline stage to an operation frequency when the present pipeline stage is about to cease, such that the power consumption of the pipeline module circuit structure is effectively reduced.

Abstract: A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to generate a corresponding varying state, and the clock gating circuit is capable of selectively withholding a triggering clock to at least one state unit according only to an initial state, such that the selected state unit(s) will not be triggered by the triggering clock while the rest of the state units are triggered by the triggering clock to update their corresponding states.

Abstract: An inquiring apparatus and method thereof is provided for assisting the CPU to inquire the state of the peripheral device. First, stop outputting the clock to the CPU. Afterwards, output a read cycle to the peripheral device. Then, receive a current state of the peripheral device in response to the read cycle. Compare the current state with the expected state. Output the clock to the CPU again if the current state and the expected state are the same.

Abstract: A method for solving intermission of streaming data. A digital controller is used to transmit streaming data stored in a storage unit. The digital controller includes a base recording unit and a trigger recorder. The method comprises steps of (a) writing an initial address of a streaming data to the base recording unit when the streaming data is being transmitted; (b) changing a content value of the trigger recorder, and proceeding to the step (a) and a step (c) simultaneously; (c) transmitting a corresponding streaming data according to one of the initial address(es) stored in the base recording unit by the digital controller; and (d) proceeding to the step (c) when the trigger recorder indicates that there are data remained to be transmitted.

Abstract: A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to generate a corresponding varying state, and the clock gating circuit is capable of selectively withholding a triggering clock to at least one state unit according only to an initial state, such that the selected state unit(s) will not be triggered by the triggering clock while the rest of the state units are triggered by the triggering clock to update their corresponding states.

Abstract: A pipeline module circuit structure with reduced power consumption and a method for operating the pipeline module circuit structure are provided. The pipeline module circuit structure comprises a plurality of pipeline stages and a clock generator, each of the pipeline stages connected to adjacent pipeline stages through a bus. A clock controller is installed in each of the pipeline stages, so as to set the clock frequency of a preceding pipeline stage to an idle frequency or stop when a present pipeline stage starts to operate and to set the clock frequency of a next pipeline stage to an operation frequency when the present pipeline stage is about to cease, such that the power consumption of the pipeline module circuit structure is effectively reduced.

Abstract: A telephone keyboard structure for making connections through static induction or touch induction control, which includes a key pad and a numbered transparent face plate with a thin slot defined therebetween for insertion therein of a picture, photo, or printed advertising card.