Patents by Inventor Yung-Huei Lee

Yung-Huei Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200343279
    Abstract: A method for forming a high dielectric constant (high-?) dielectric layer on a substrate including performing a pre-clean process on a surface of the substrate. A chloride precursor is introduced on the surface. An oxidant is introduced to the surface to form the high-? dielectric layer on the substrate. A chlorine concentration of the high-? dielectric layer is lower than about 8 atoms/cm3.
    Type: Application
    Filed: July 8, 2020
    Publication date: October 29, 2020
    Inventors: Tsung-Han Tsai, Horng-Huei Tseng, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng, Hsin-Chieh Huang
  • Patent number: 10720460
    Abstract: A method for forming a high dielectric constant (high-?) dielectric layer on a substrate including performing a pre-clean process on a surface of the substrate. A chloride precursor is introduced on the surface. An oxidant is introduced to the surface to form the high-? dielectric layer on the substrate. A chlorine concentration of the high-? dielectric layer is lower than about 8 atoms/cm3.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Horng-Huei Tseng, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng, Hsin-Chieh Huang
  • Patent number: 10636824
    Abstract: A method for forming a high dielectric constant (high-?) dielectric layer on a substrate including performing a pre-clean process on a surface of the substrate. A chloride precursor is introduced on the surface. An oxidant is introduced to the surface to form the high-? dielectric layer on the substrate. A chlorine concentration of the high-? dielectric layer is lower than about 8 atoms/cm3.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Horng-Huei Tseng, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng, Hsin-Chieh Huang
  • Publication number: 20200127024
    Abstract: A method for forming a high dielectric constant (high-?) dielectric layer on a substrate including performing a pre-clean process on a surface of the substrate. A chloride precursor is introduced on the surface. An oxidant is introduced to the surface to form the high-? dielectric layer on the substrate. A chlorine concentration of the high-? dielectric layer is lower than about 8 atoms/cm3.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Tsung-Han Tsai, Horng-Huei Tseng, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng, Hsin-Chieh Huang
  • Publication number: 20200013810
    Abstract: A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 9, 2020
    Inventors: Yun-Wei Cheng, Horng Huei Tseng, Chao-Hsiung Wang, Chun-Hao Chou, Tsung-Han Tsai, Kuo-Cheng Lee, Tzu-Hsuan Hsu, Yung-Lung Hsu
  • Patent number: 10475742
    Abstract: A method of forming a semiconductor device structure includes: forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and wherein the forming the first conductive structure includes manipulating process conditions so as to promote formation of the twin boundaries resulting in a promoted density of twin boundaries such that the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted density of twin boundaries, the unpromoted density being less than the promoted density and such that the first conductive structure has a resistance which is substantially the same as the second conductive structure.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh, Tsung-Cheng Chan, Chun-Lung Huang
  • Patent number: 10367965
    Abstract: An image scanning device includes an upper shell, a feeding shaft pivotally connected to the upper shell, a feeding roller mounted around the feeding shaft, a sensing roller, a motor, a lower shell pivotally covered to the upper shell, a plurality of springs and a contact image sensor. The sensing roller is mounted around the feeding shaft. The motor is connected with the feeding shaft. The motor drives the feeding shaft to rotate in different speeds. The plurality of the springs are mounted to the lower shell. The contact image sensor is mounted to the plurality of the springs. A top surface of the contact image sensor is capable of abutting against lower portions of outer surfaces of the feeding roller and the sensing roller by virtue of the plurality of the springs elastically abutting against a bottom surface of the contact image sensor.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 30, 2019
    Assignee: Foxlink Image Technology Co., Ltd.
    Inventors: Chun Huei Cheng, Chang Hsien Sung, Yung Wen Lee
  • Publication number: 20190157320
    Abstract: A method for forming a high dielectric constant (high-?) dielectric layer on a substrate including performing a pre-clean process on a surface of the substrate. A chloride precursor is introduced on the surface. An oxidant is introduced to the surface to form the high-? dielectric layer on the substrate. A chlorine concentration of the high-? dielectric layer is lower than about 8 atoms/cm3.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 23, 2019
    Inventors: Tsung-Han Tsai, Horng-Huei Tseng, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng
  • Patent number: 10283450
    Abstract: A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries. The forming the conductive structure includes: manipulating process conditions so as to promote formation of the twin boundaries and yet control a density of the twin boundaries to be outside a range for which a portion of a curve is an asymptote of a constant value, the curve representing values of an atomic migration ratio corresponding to values of the density of the twin boundaries.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh, Tsung-Cheng Chan, Chun-Lung Huang
  • Publication number: 20190103351
    Abstract: A method of forming a semiconductor device structure includes: forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and wherein the forming the first conductive structure includes manipulating process conditions so as to promote formation of the twin boundaries resulting in a promoted density of twin boundaries such that the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted density of twin boundaries, the unpromoted density being less than the promoted density and such that the first conductive structure has a resistance which is substantially the same as the second conductive structure.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Jian-Hong LIN, Chwei-Ching CHIU, Yung-Huei LEE, Chien-Neng LIAO, Yu-Lun CHUEH, Tsung-Cheng CHAN, Chun-Lung HUANG
  • Publication number: 20180269148
    Abstract: A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 20, 2018
    Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Hui LEE, Yung-Sheng HUANG, Yung-Huei LEE
  • Patent number: 9941159
    Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Shiou-Fan Chen, Chwei-Ching Chiu, Yung-Huei Lee
  • Publication number: 20170338178
    Abstract: A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries. The forming the conductive structure includes: manipulating process conditions so as to promote formation of the twin boundaries and yet control a density of the twin boundaries to be outside a range for which a portion of a curve is an asymptote of a constant value, the curve representing values of an atomic migration ratio corresponding to values of the density of the twin boundaries.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Inventors: Jian-Hong LIN, Chwei-Ching CHIU, Yung-Huei LEE, Chien-Neng LIAO, Yu-Lun CHUEH, Tsung-Cheng CHAN, Chun-Lung HUANG
  • Patent number: 9761523
    Abstract: A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive structure formed over the substrate. The conductive structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 ?m?1 to about 250 ?m?1.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Chwei-Ching Chiu, Yung-Huei Lee, Chien-Neng Liao, Yu-Lun Chueh, Tsung-Cheng Chan, Chun-Lung Huang
  • Publication number: 20170053865
    Abstract: A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive structure formed over the substrate. The conductive structure includes twin boundaries, and a density of the twin boundaries is in a range from about 25 ?m?1 to about 250 ?m?1.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Jian-Hong LIN, Chwei-Ching CHIU, Yung-Huei LEE, Chien-Neng LIAO, Yu-Lun CHUEH, Tsung-Cheng CHAN, Chun-Lung HUANG
  • Publication number: 20160372368
    Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Shiou-Fan CHEN, Chwei-Ching CHIU, Yung-Huei LEE
  • Patent number: 9449919
    Abstract: A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion. The first interconnect portion has a width and a length. The second interconnect portion has a width less than the length of the first interconnect portion. The second interconnect portion is connected to the first interconnect portion. The third interconnect portion has a width less than the width of the second interconnect portion. The third interconnect portion is connected to the second interconnect portion.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Hong Lin, Hsin-Chun Chang, Shiou-Fan Chen, Chwei-Ching Chiu, Yung-Huei Lee
  • Publication number: 20160240472
    Abstract: A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion. The first interconnect portion has a width and a length. The second interconnect portion has a width less than the length of the first interconnect portion. The second interconnect portion is connected to the first interconnect portion. The third interconnect portion has a width less than the width of the second interconnect portion. The third interconnect portion is connected to the second interconnect portion.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Inventors: Jian-Hong LIN, Hsin-Chun CHANG, Shiou-Fan CHEN, Chwei-Ching CHIU, Yung-Huei LEE
  • Patent number: 8946874
    Abstract: Integrated Circuits and methods for reducing thermal neutron soft error rate (SER) of a digital circuit are provided by doping a protection layer on top of the metal layer and in physical contact with the metal layer of the digital circuit, wherein the protection layer is doped with additional thermal neutron absorbing material. The thermal neutron absorbing material can be selected from the group consisting of Gd, Sm, Cd, B, and combinations thereof. The protection layer may comprise a plurality of sub-layers among which a plurality of them containing additional thermal neutron absorbing material.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Huei Lee, Chou-Jie Tsai, Chia-Fang Wu, Wei-Cheng Chu
  • Patent number: 8633109
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate. The method includes forming a portion of an interconnect structure over the substrate. The portion of the interconnect structure has an opening. The method includes obtaining a boron-containing gas that is free of a boron-10 isotope. The method includes filling the opening with a conductive material to form a contact. The filling of the opening is carried out using the boron-containing gas. Also provided is a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an interconnect structure formed over the substrate. The semiconductor device includes a conductive contact formed in the interconnect structure. The conductive contact has a material composition that includes Tungsten and Boron, wherein the Boron is a 11B-enriched Boron.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: January 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Huei Lee, Chou-Jie Tsai, Chia-Fang Wu, Jang Jung Lee, Wei-Cheng Chu, Dong Gui