Abstract: A flat package includes a die, a cover layer, multiple conductive contacts, and a dielectric protection layer. The cover layer includes a molding layer. The molding layer covers the die yet exposes multiple pads on the die. The conductive contacts are formed on a surface of a molding layer facing a same side as the pads, and the conductive contacts are electrically connected to the pads respectively. The dielectric protection layer partially covers surfaces of the conductive contacts and of the molding layer. The flat package can be easily manufactured, as manufacturing the flat package consumes little time and cost. The flat package is small in its overall size, allowing the flat package to fit into a product for use.

Abstract: A semiconductor package structure and a byproduct of a semiconductor component. The semiconductor package structure including a lead frame, a nanotwinned metal layer, a semiconductor component and a molding layer. The lead frame includes a supporting part and a circuit part. The nanotwinned metal layer is located on the supporting part. The semiconductor component is disposed on the nanotwinned metal layer. The nanotwinned metal layer is located between the supporting part and the semiconductor component. The semiconductor component is electrically connected to the circuit part. The molding layer covers the nanotwinned metal layer and the semiconductor component.

Abstract: A method for manufacturing a packaged component with a composite pin structure has: dividing a substrate into a body area and a pin area, wherein a chip is arranged on the body area of the substrate and is electrically connected to conductive layers on the opposite surfaces of the substrate. The pin area is pre-defined with multiple parallel pin positions. After the electrical connection of the chip is completed in the body area, a cutting tool is used to cut along the peripheries of the body area and the pin positions to obtain a packaged component body and multiple pins. Each of the pins is integrally formed by the substrate of the packaged component body without using a conventional lead frame.

Abstract: A package with embedded traces has a main body and multiple leads. The main body includes an insulating body, a die in the insulating body, and multiple conductive traces in the insulating body, wherein the die is electrically connected to the insulating body. The multiple leads extend outward from the main body. Each of the multiple leads includes a lead carrier and two conducting layers that are formed on opposite surfaces of the lead carrier and electrically connected to the respective conductive trace so that the two conducting layers are electrically connected to the die, wherein at least one of the two conducting layers is embedded in the lead carrier.

Abstract: A die of the package device is covered by an encapsulation layer, a plurality of lead portions are configured on the bottom surface of the encapsulation layer, a side portion of each lead portion is also exposed on a side surface of the encapsulation layer, and thereby the package device is used as a side-wettable package device; wherein, in a process of manufacturing the package device, a conductive electroplated conducting layer is formed on the surface of the encapsulation layer, and the electroplated conducting layer is used to conduct electric power required during an electroplating process. After the electroplating process is completed, the electroplated conducting layer can be used as a heat dissipation layer for the package device. The heat dissipation layer completely covers the surface of the package device so as to increase heat dissipation area and to be attached by a heat sink.

Abstract: The present invention provides a wafer level chip scale package (WLCSP) unit; the WLCSP unit includes a die, a dielectric layer, and a bottom metal layer; the die has a substrate and an active surface; multiple pads are mounted on the active surface, and a soldering layer is mounted on a surface of each of the pads; the dielectric layer covers an upper part of four lateral surfaces of the die, exposing a lower part of the four lateral surfaces of the die; the bottom metal layer is mounted on a bottom surface of the substrate; the bottom metal layer protects a bottom surface of the dies, dissipates heat generated by the dies, and also protects the dies from external electromagnetic interferences (EMI).

Abstract: A method for manufacturing a packaged component with a composite pin structure has: dividing a substrate into a body area and a pin area, wherein a chip is arranged on the body area of the substrate and is electrically connected to conductive layers on the opposite surfaces of the substrate. The pin area is pre-defined with multiple parallel pin positions. After the electrical connection of the chip is completed in the body area, a cutting tool is used to cut along the peripheries of the body area and the pin positions to obtain a packaged component body and multiple pins. Each of the pins is integrally formed by the substrate of the packaged component body without using a conventional lead frame.

Abstract: An optical communication package structure includes a wiring structure, at least one via structure, a redistribution structure, at least one optical device and at least one electrical device. The wiring structure includes a main portion and a conductive structure disposed on an upper surface of the main portion. The main portion defines at least one through hole extending through the main portion. The via structure is disposed in the at least one through hole of the main portion and electrically connected to the conductive structure. The redistribution structure is disposed on a lower surface of the main portion and electrically connected to the via structure. The optical device is disposed adjacent to the upper surface of the main portion and electrically connected to the conductive structure. The electrical device is disposed on and electrically connected to the conductive structure.

Abstract: An optical communication package structure includes a wiring structure, at least one via structure, a redistribution structure, at least one optical device and at least one electrical device. The wiring structure includes a main portion and a conductive structure disposed on an upper surface of the main portion. The main portion defines at least one through hole extending through the main portion. The via structure is disposed in the at least one through hole of the main portion and electrically connected to the conductive structure. The redistribution structure is disposed on a lower surface of the main portion and electrically connected to the via structure. The optical device is disposed adjacent to the upper surface of the main portion and electrically connected to the conductive structure. The electrical device is disposed on and electrically connected to the conductive structure.

Abstract: An optical communication package structure includes a wiring structure, at least one via structure, a redistribution structure, at least one optical device and at least one electrical device. The wiring structure includes a main portion and a conductive structure disposed on an upper surface of the main portion. The main portion defines at least one through hole extending through the main portion. The via structure is disposed in the at least one through hole of the main portion and electrically connected to the conductive structure. The redistribution structure is disposed on a lower surface of the main portion and electrically connected to the via structure. The optical device is disposed adjacent to the upper surface of the main portion and electrically connected to the conductive structure. The electrical device is disposed on and electrically connected to the conductive structure.

Abstract: An optical communication package structure includes a wiring structure, at least one via structure, a redistribution structure, at least one optical device and at least one electrical device. The wiring structure includes a main portion and a conductive structure disposed on an upper surface of the main portion. The main portion defines at least one through hole extending through the main portion. The via structure is disposed in the at least one through hole of the main portion and electrically connected to the conductive structure. The redistribution structure is disposed on a lower surface of the main portion and electrically connected to the via structure. The optical device is disposed adjacent to the upper surface of the main portion and electrically connected to the conductive structure. The electrical device is disposed on and electrically connected to the conductive structure.

Abstract: A semiconductor wafer includes a substrate structure, a first insulation layer, a conductive layer and a second insulation layer. The substrate structure defines a via. The first insulation layer covers a surface of the substrate structure. The first insulation layer extends into the via, covers a lateral wall of the via and exposes a bottom surface at a bottom of the via. The conductive layer covers the first insulation layer and the bottom surface exposed by the first insulation layer. The second insulation layer covers the conductive layer. A warpage of the semiconductor wafer is less than 550 micrometers.

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract: The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area.

Abstract: The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area.

Abstract: A closure device for a drain pipeline includes an outer sleeve, an inner sleeve mounted in the outer sleeve, and a closure member. The outer sleeve is adapted to be installed between a drain of a sink or washbasin and a drainpipe. A flow port is defined in the inner sleeve. The closure member is movably supported in the inner sleeve in a vertical direction. The closure member is normally biased by a spring to close the flow port so as to block odor from flowing into an indoor space, and the closure member is moved downwards to open the flow port when draining water into the outer sleeve.

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract: A closure device for a drain pipeline includes an outer sleeve, an inner sleeve mounted in the outer sleeve, and a closure member. The outer sleeve is adapted to be installed between a drain of a sink or washbasin and a drainpipe. A flow port is defined in the inner sleeve. The closure member is movably supported in the inner sleeve in a vertical direction. The closure member is normally biased by a spring to close the flow port so as to block odor from flowing into an indoor space, and the closure member is moved downwards to open the flow port when draining water into the outer sleeve.