Patents by Inventor Yung-Hui YU

Yung-Hui YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11762768
    Abstract: A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: September 19, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yung-Hui Yu, Chih-Wea Wang
  • Patent number: 11734212
    Abstract: A bus interconnection system and a method for detecting bad routing by the same are provided. The bus interconnection system includes a master node, destination nodes, and a first order switch node. The destination nodes include slave nodes, the bus interconnection system assigns an identification symbol to each of the destination nodes, and adds a destination identification symbol to data sent to the slave nodes by the master node through the first order switch node. When the first order switch node receives the data, the first order switch node updates the destination identification symbol of the data according to a payload of the data, and when one of the destination nodes receives the data, the one of the destination nodes determines whether a bad routing occurs by checking whether the destination identification symbol is equal to the identification symbol assigned to the destination node that receives the data.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: August 22, 2023
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Yung-Hui Yu
  • Publication number: 20220405224
    Abstract: A bus interconnection system and a method for detecting bad routing by the same are provided. The bus interconnection system includes a master node, destination nodes, and a first order switch node. The destination nodes include slave nodes, the bus interconnection system assigns an identification symbol to each of the destination nodes, and adds a destination identification symbol to data sent to the slave nodes by the master node through the first order switch node. When the first order switch node receives the data, the first order switch node updates the destination identification symbol of the data according to a payload of the data, and when one of the destination nodes receives the data, the one of the destination nodes determines whether a bad routing occurs by checking whether the destination identification symbol is equal to the identification symbol assigned to the destination node that receives the data.
    Type: Application
    Filed: November 12, 2021
    Publication date: December 22, 2022
    Inventor: YUNG-HUI YU
  • Publication number: 20210209018
    Abstract: A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.
    Type: Application
    Filed: December 29, 2020
    Publication date: July 8, 2021
    Inventors: Yung-Hui YU, Chih-Wea WANG
  • Publication number: 20140215284
    Abstract: A dynamic scaling processor device and processing method thereof, having a timing decoder, a multi-cycle controller, a correction flip-flop. The timing decoder is provided with a plurality of cycles therein, to receive a plurality of instructions, to select corresponding cycles as its predetermined cycles based on type of each instruction, and output the predetermined cycles and its corresponding instructions to the multi-cycle controller. The multi-cycle controller computes results of the instructions based on the predetermined cycles or a single cycle, and outputs them to the correction flip-flop. The error detection flip-flop utilizes a first clock signal and a stalled second clock signal, to sample a same result, and correct the results when outcomes of samplings are different.
    Type: Application
    Filed: August 6, 2013
    Publication date: July 31, 2014
    Applicant: National Chung Cheng University
    Inventors: Tien-Fu CHEN, Shu-Hsuan CHOU, Po-Hao WANG, Yung-Hui YU