Abstract: A process sequence for forming a MOSFET device featuring a high k gate insulator layer, wherein the use of the high k gate insulator layer requires no additional photolithographic procedures, has been developed. After deposition of a high k gate insulator layer followed by the definition of an overlying conductive gate structure, an insulator layer is deposited. An anisotropic dry etch procedure is then employed to first define offset insulator spacers on the sides of the conductive gate structure, then to selectively remove the unwanted portions of the high k gate insulator layer. The use of the high k gate insulator layer provides a thin gate insulator layer with less risk of leakage when compared to counterpart gate insulator layers such as silicon dioxide, while the integration of the definition of the offset insulator spacer step and of the high k gate layer removal procedure, results in fabrication cost savings.

Abstract: A method for compensating CD variations across a semiconductor process wafer surface in a plasma etching process including a semiconductor wafer having a process surface comprising patterned features; carrying out a first plasma etching process wherein the semiconductor wafer is heated to at least two selectively controllable temperature zones; determining a first dimensional variation of etched features with respect to reference dimensions over predetermined areas of the process surface including the two selectively controllable temperature zones; determining operating temperatures for the two selectively controllable temperature zones to achieve a targeted dimensional variation change in the first dimensional variation to achieve a desired second dimensional variation; plasma etching the process surface to the desired operating temperatures; and, determining an actual dimensional variation change for use in at least one subsequent plasma etching process.