Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.

Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: A display includes an outer frame, a supporting frame, a display module, and a covering member. The supporting frame is accommodated in the outer frame. The display module is disposed on a supporting member of the supporting frame. The supporting member extends toward a display region of the display module from the supporting frame. On a first surface of the display module, a projection area of the supporting member and a projection area of an first optical film of the display module are partially overlapped with each other. A third surface of the covering member is closely attached to a second optical film of the display module. The covering member has an extension portion. The extension portion extends from a fourth surface opposite to the third surface toward a direction away from the third surface, and the extension portion is coplanar with the outer side surface of the outer frame.

Abstract: The display system comprising a main control module and a display module is provided. The main control module comprises a display driving circuit and a timing control circuit. The display driving circuit is used to output a display driving signal. The timing control circuit is coupled to the display driving circuit to receive the display driving signal, and convert the display driving signal into a digital signal. The display module comprises a first display panel to an N-th display panel, coupled to the timing control circuit and receiving the digital signal, so as to display corresponding multimedia content according to the digital signal, wherein N is a positive integer greater than 1, and the main control module is independently coupled to the display module.

Abstract: A method of manufacturing an electronic device, including the following steps, is provided. A first dielectric layer and a second dielectric layer are provided. The first dielectric layer has a first surface and a second surface opposite to each other, and the second dielectric layer has a third surface and a fourth surface opposite to each other. A first unit is formed on the first surface or the second surface of the first dielectric layer. The first dielectric layer and the second dielectric layer are combined to form a substrate structure. The second surface of the first dielectric layer faces the third surface of the second dielectric layer. A dielectric loss of the first unit is less than a dielectric loss of the first dielectric layer. The method of manufacturing the electronic device of the embodiment of the disclosure can reduce the dielectric loss by using the unit.

Abstract: A trajectory predicting method and a computing system for trajectory prediction are provided. In the method, feature extraction is respectively performed on past trajectories of multiple target objects through an encoder to generate first trajectory information of the target objects. A pooling process is performed on the first trajectory information of the target objects to generate second trajectory information of the target objects. The second trajectory information of each target object includes location relationships relative to other target objects. Third trajectory information is obtained from the past trajectories of the target objects. The third trajectory information includes a moving direction, scene information, and/or a moving mode. The predicted trajectories of the target objects are generated according to the second trajectory information and the third trajectory information through a decoder. Accordingly, the accuracy of prediction can be improved.

Abstract: A display includes an outer frame, a supporting frame, a display module, and a covering member. The supporting frame is accommodated in the outer frame. The display module is disposed on a supporting member of the supporting frame. The supporting member extends toward a display region of the display module from the supporting frame. On a first surface of the display module, a projection area of the supporting member and a projection area of an first optical film of the display module are partially overlapped with each other. A third surface of the covering member is closely attached to a second optical film of the display module. The covering member has an extension portion. The extension portion extends from a fourth surface opposite to the third surface toward a direction away from the third surface, and the extension portion is coplanar with the outer side surface of the outer frame.

Abstract: A circuit verification method, including the following steps: inputting a circuit design data to a processor, wherein the circuit design data includes a plurality of logic circuits and a plurality of detection nodes, each logic circuit includes a control terminal and a plurality of input terminals, and is configured to output a signal to the detection node; inputting a plurality of first-stage property command to the processor to generate a plurality of first-stage formal commands, and the first-stage formal commands are configured to verify whether signals of the detection nodes remain stable when a signals of the control terminal of each of the logic circuits does not changed; finding a first part of the detection nodes by a formal method according to the first-stage formal commands; and finding a second part of the detection nodes by a formal method.

Abstract: A buck converter includes a quick response circuit, a compensator coupled to an output node, an interleaving logic circuit coupled to the compensator, a plurality of on-time generators, a plurality of OR gates coupled to the corresponding on-time generator, a plurality of power stages coupled to the corresponding OR gates, a plurality of inductors and an output capacitor. Each on-time generator is coupled to the interleaving logic circuit, an input node and the output node. The quick response circuit includes a voltage droop sensor coupled to the output node, a load frequency sensor coupled to the output node, a quick response signal generator coupled to the voltage droop sensor, a maximum quick response signal generator coupled to the voltage droop sensor and the load frequency sensor, an AND gate coupled to the quick response signal generator, the maximum quick response signal generator and the plurality of OR gates.

Abstract: The display system comprising a main control module and a display module is provided. The main control module comprises a display driving circuit and a timing control circuit. The display driving circuit is used to output a display driving signal. The timing control circuit is coupled to the display driving circuit to receive the display driving signal, and convert the display driving signal into a digital signal. The display module comprises a first display panel to an N-th display panel, coupled to the timing control circuit and receiving the digital signal, so as to display corresponding multimedia content according to the digital signal, wherein N is a positive integer greater than 1, and the main control module is independently coupled to the display module.

Abstract: A buck converter includes a quick response circuit, a compensator coupled to an output node, an interleaving logic circuit coupled to the compensator, a plurality of on-time generators, a plurality of OR gates coupled to the corresponding on-time generator, a plurality of power stages coupled to the corresponding OR gates, a plurality of inductors and an output capacitor. Each on-time generator is coupled to the interleaving logic circuit, an input node and the output node. The quick response circuit includes a voltage droop sensor coupled to the output node, a load frequency sensor coupled to the output node, a quick response signal generator coupled to the voltage droop sensor, a maximum quick response signal generator coupled to the voltage droop sensor and the load frequency sensor, an AND gate coupled to the quick response signal generator, the maximum quick response signal generator and the plurality of OR gates.

Abstract: A display includes an outer frame, a supporting frame, a display module, and a covering member. The supporting frame is accommodated in the outer frame. The display module is disposed on a supporting member of the supporting frame. The supporting member extends toward a display region of the display module from the supporting frame. On a first surface of the display module, a projection area of the supporting member and a projection area of an first optical film of the display module are partially overlapped with each other. A third surface of the covering member is closely attached to a second optical film of the display module. The covering member has an extension portion. The extension portion extends from a fourth surface opposite to the third surface toward a direction away from the third surface, and the extension portion is coplanar with the outer side surface of the outer frame.

Abstract: An air purifier is disclosed and includes a housing, a cover, a filter assembly, and a fan. The housing includes a casing and a shell which are detachable from each other, the casing has a venting portion. The cover has at least one breathable part. The filter assembly is configured in a space defined by the casing and the cover. The filter assembly includes a transformable body and at least one filter. The transformable body has two passage portions. The filter is located between the two passage portions. The transformable body is configured to be transformable to change airflow through the filter. The venting portion, the two passage portions, the breathable part are coupled in fluid communication. The fan is disposed in the housing and configured to generate airflow. The filter assembly is suitable for different situations of ventilating for fixed-locations and being worn for protection from smoke.

Abstract: A switching regulator which has load transient quick response ability includes at least one power stage circuit and a control circuit. The control circuit includes a pulse width modulation (PWM) signal generation circuit and a quick response (QR) signal generation circuit. The PWM signal generation circuit generates a PWM signal according to an output voltage and a QR signal, to control a power switch of the corresponding power stage circuit, thus converting an input voltage to the output voltage. The QR signal generation circuit includes a differentiator circuit and a comparison circuit. The differentiator circuit performs a differential operation on a voltage sensing signal related to the output voltage, to generate a differential signal. The comparison circuit compares the differential signal with a QR threshold signal, such that when the differential signal exceeds the QR signal, the PWM signal generation circuit performs a QR procedure.

Abstract: An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

Abstract: A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.

Abstract: A switching regulator which has load transient quick response ability includes at least one power stage circuit and a control circuit. The control circuit includes a pulse width modulation (PWM) signal generation circuit and a quick response (QR) signal generation circuit. The PWM signal generation circuit generates a PWM signal according to an output voltage and a QR signal, to control a power switch of the corresponding power stage circuit, thus converting an input voltage to the output voltage. The QR signal generation circuit includes a differentiator circuit and a comparison circuit. The differentiator circuit performs a differential operation on a voltage sensing signal related to the output voltage, to generate a differential signal. The comparison circuit compares the differential signal with a QR threshold signal, such that when the differential signal exceeds the QR signal, the PWM signal generation circuit performs a QR procedure.

Abstract: The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.

Abstract: A method of detecting a circuit malfunction in a register transfer level, RTL, design stage is disclosed. The method comprises obtaining signal points of each register from a circuit model based on the RTL design stage, generating a property list according to the signal points of each register, wherein the property list includes a property to be verified for each signal point, performing a formal verification operation according to the circuit model and the property list, to determine whether the property of the property list for each signal point in the circuit model is true, and generating a circuit malfunction result according to the signal point whose property is not true.

Abstract: A method of detecting a circuit malfunction in a register transfer level, RTL, design stage is disclosed. The method comprises obtaining signal points of each register from a circuit model based on the RTL design stage, generating a property list according to the signal points of each register, wherein the property list includes a property to be verified for each signal point, performing a formal verification operation according to the circuit model and the property list, to determine whether the property of the property list for each signal point in the circuit model is true, and generating a circuit malfunction result according to the signal point whose property is not true.