Patents by Inventor Yung-jr Hung

Yung-jr Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240061308
    Abstract: Optical devices and methods of fabricating thereof that include providing two different optical paths: a first optical path including a first waveguide core and a first cladding layer adjacent the first waveguide core; and a second optical path including a second waveguide core and a second cladding layer adjacent the second waveguide core. A thermo-optic coefficient (TOC) of the first waveguide core and a TOC of the first cladding layer have a same sign, for example positive, and a sign of a TOC of the second waveguide core is different than a sign of a TOC of the second cladding layer, for example, one positive and one negative. The paths may be in an Mach-Zehnder Interferometer (MZI).
    Type: Application
    Filed: February 8, 2023
    Publication date: February 22, 2024
    Inventors: Tzu-Hsiang YEN, Yung-Jr HUNG, Tai-Chun HUANG
  • Publication number: 20240036261
    Abstract: A broadband ring resonator includes a first waveguide and a second waveguide. The first waveguide is a closed loop having a first coupling section having a first width and a first curvature radius. The second waveguide includes a first section, a second coupling section, and a second section which are connected in sequence. The second coupling section has a second width and a second curvature radius. Coupling ratios of the second waveguide coupled to the first waveguide within a broadband have a similarity to each other. A coupling angle is respectively between two ends of the first coupling section and between two ends of the second coupling section, and the first and second coupling sections are separated by a coupling gap. The second curvature radius is greater than the first curvature radius. A ratio of the first width with respect to the second width ranges from 1.3 to 1.7.
    Type: Application
    Filed: December 19, 2022
    Publication date: February 1, 2024
    Inventors: Yung-Jr HUNG, Cheng-Hsuan WU
  • Publication number: 20230400639
    Abstract: Disclosed are edge couplers having a high coupling efficiency and low polarization dependent loss, and methods of making the edge couplers. In one embodiment, a semiconductor device for optical coupling is disclosed. The semiconductor device includes: a substrate; an optical waveguide over the substrate; and a plurality of layers over the optical waveguide. The plurality of layers includes a plurality of coupling pillars disposed at an edge of the semiconductor device. The plurality of coupling pillars form an edge coupler configured for optically coupling the optical waveguide to an optical fiber placed at the edge of the semiconductor device.
    Type: Application
    Filed: August 9, 2023
    Publication date: December 14, 2023
    Inventors: Min-Hsiang HSU, Chewn-Pu Jou, Chan-Hong Chern, Cheng-Tse Tang, Yung-Jr Hung, Lan-Chou Cho
  • Patent number: 11796739
    Abstract: Disclosed are edge couplers having a high coupling efficiency and low polarization dependent loss, and methods of making the edge couplers. In one embodiment, a semiconductor device for optical coupling is disclosed. The semiconductor device includes: a substrate; an optical waveguide over the substrate; and a plurality of layers over the optical waveguide. The plurality of layers includes a plurality of coupling pillars disposed at an edge of the semiconductor device. The plurality of coupling pillars form an edge coupler configured for optically coupling the optical waveguide to an optical fiber placed at the edge of the semiconductor device.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Hsiang Hsu, Chewn-Pu Jou, Chan-Hong Chern, Cheng-Tse Tang, Yung-Jr Hung, Lan-Chou Cho
  • Publication number: 20230228944
    Abstract: A waveguide division multiplexer and demultiplexer includes a first-stage Mach-Zehnder interferometer (MZI) and two second-stage MZIs. The first-stage MZI includes two input ends and two output ends, in which one of the inputs is configured to receive an input optical beam with a first center wavelength and a second center wavelength, and the output ends are configured to respectively transmit first-stage output optical beams respectively with the first center wavelength and the second center wavelength. One input terminals of the second-stage MZI are configured to respectively receive the first-stage output optical beams, and one output terminals of the second-stage MZI are configured to transmit second-stage output optical beams with the first and second center wavelengths, respectively. Each second-stage MZI is configured in cross-state condition.
    Type: Application
    Filed: September 20, 2022
    Publication date: July 20, 2023
    Inventors: Yung-Jr HUNG, Tzu-Hsiang YEN
  • Publication number: 20230061568
    Abstract: Disclosed are edge couplers having a high coupling efficiency and low polarization dependent loss, and methods of making the edge couplers. In one embodiment, a semiconductor device for optical coupling is disclosed. The semiconductor device includes: a substrate; an optical waveguide over the substrate; and a plurality of layers over the optical waveguide. The plurality of layers includes a plurality of coupling pillars disposed at an edge of the semiconductor device. The plurality of coupling pillars form an edge coupler configured for optically coupling the optical waveguide to an optical fiber placed at the edge of the semiconductor device.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Min-Hsiang Hsu, Chewn-Pu Jou, Chan-Hong Chern, Cheng-Tse Tang, Yung-Jr Hung, Lan-Chou Cho
  • Publication number: 20220155074
    Abstract: A silicon photonic integrated circuit is provided, which includes a first optical power splitter, a second optical power splitter, a first grating coupler and a second grating coupler. The first optical power splitter has an input, a first output and a second output, in which the input is configured to receive an inputted beam, and the first output is configured to output a returned beam. The second optical power splitter has an input, a first output and a second output, in which the input is coupled to the second output of the first optical power splitter. The first and second grating couplers are respectively coupled to the first and second outputs of the second optical power splitter, and are configured to optically couple two opposite ends of a fiber coil, respectively.
    Type: Application
    Filed: December 17, 2020
    Publication date: May 19, 2022
    Inventor: Yung-Jr HUNG
  • Patent number: 11313682
    Abstract: A silicon photonic integrated circuit is provided, which includes a first optical power splitter, a second optical power splitter, a first grating coupler and a second grating coupler. The first optical power splitter has an input, a first output and a second output, in which the input is configured to receive an inputted beam, and the first output is configured to output a returned beam. The second optical power splitter has an input, a first output and a second output, in which the input is coupled to the second output of the first optical power splitter. The first and second grating couplers are respectively coupled to the first and second outputs of the second optical power splitter, and are configured to optically couple two opposite ends of a fiber coil, respectively.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 26, 2022
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventor: Yung-Jr Hung
  • Patent number: 10916915
    Abstract: A distributed feedback (DFB) semiconductor laser device includes an active layer, a first grating layer and a second grating. The first grating layer has a first grating structure with a first grating period. The second grating layer has a second grating structure with a second grating period substantially different from the first grating period. The active layer, the first grating layer and the second grating layer are vertically stacked, and the equivalent grating period of the DFB semiconductor laser device is (2×P1×P2)/(P1+P2), where P1 and P2 respectively represent the first grating period and the second grating period.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 9, 2021
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Yung-Jr Hung, Yen-Chieh Wang, Ping-Feng Hsieh, Wei Lin
  • Publication number: 20200203925
    Abstract: A distributed feedback (DFB) semiconductor laser device includes an active layer, a first grating layer and a second grating. The first grating layer has a first grating structure with a first grating period. The second grating layer has a second grating structure with a second grating period substantially different from the first grating period. The active layer, the first grating layer and the second grating layer are vertically stacked, and the equivalent grating period of the DFB semiconductor laser device is (2×P1×P2)/(P1+P2), where P1 and P2 respectively represent the first grating period and the second grating period.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Yung-Jr HUNG, Yen-Chieh WANG, Ping-Feng HSIEH
  • Patent number: 10042173
    Abstract: A laser interference lithography system with flat-top intensity profile comprises a laser source for emitting a coherent laser beam, a first beam expander for adjusting the coherent laser beam size, a refractive beam shaper for converting a Gaussian intensity profile inherent to the coherent laser beam into a flat-top one and outputting a first collimated laser beam, a second beam expander for receiving the first collimated laser beam and outputting a second collimated laser beam, a sample holder for holding a substrate, and at least one reflector for reflecting the second collimated laser beam to generate a third collimated laser beam. The second and third collimated laser beams are transmitted to the substrate at a predetermined angle to create an interference pattern exposed onto the substrate.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: August 7, 2018
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Yung-Jr Hung, Han-Jung Chang
  • Patent number: 9904176
    Abstract: An interference lithography device is provided with a laser source for providing a laser beam; a base thereon having a beam splitter for dividing the laser beam into a first beam portion and a second beam portion, a beam expander, a first set of reflectors, and a second set of reflectors; a set of lower reflectors; and a sample carrying stage for holding a substrate. The first beam portion and the second beam portion are respectively reflected from the second set of reflectors and then respectively reflected by the set of lower reflectors to form an interference pattern on the substrate.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: February 27, 2018
    Assignees: NATIONAL SUN YAT-SEN UNVIERSITY, LANDMARK OPTOELECTRONICS CORPORATION
    Inventors: Yung-Jr Hung, Wei Lin
  • Publication number: 20170329146
    Abstract: A laser interference lithography system with flat-top intensity profile comprises a laser source for emitting a coherent laser beam, a first beam expander for adjusting the coherent laser beam size, a refractive beam shaper for converting a Gaussian intensity profile inherent to the coherent laser beam into a flat-top one and outputting a first collimated laser beam, a second beam expander for receiving the first collimated laser beam and outputting a second collimated laser beam, a sample holder for holding a substrate, and at least one reflector for reflecting the second collimated laser beam to generate a third collimated laser beam. The second and third collimated laser beams are transmitted to the substrate at a predetermined angle to create an interference pattern exposed onto the substrate.
    Type: Application
    Filed: May 4, 2017
    Publication date: November 16, 2017
    Inventors: Yung-Jr Hung, Han-Jung Chang
  • Publication number: 20170123325
    Abstract: An interference lithography device is provided with a laser source for providing a laser beam; a base thereon having a beam splitter for dividing the laser beam into a first beam portion and a second beam portion, a beam expander, a first set of reflectors, and a second set of reflectors; a set of lower reflectors; and a sample carrying stage for holding a substrate. The first beam portion and the second beam portion are respectively reflected from the second set of reflectors and then respectively reflected by the set of lower reflectors to form an interference pattern on the substrate.
    Type: Application
    Filed: May 4, 2016
    Publication date: May 4, 2017
    Inventors: Yung-Jr HUNG, Wei LIN
  • Publication number: 20130012022
    Abstract: A method for larger-area fabrication of uniform silicon nanowire arrays is disclosed. The method includes forming a metal layer with a predetermined thickness on a substrate whose surface has a silicon material by a coating process, the metal layer selected from the group consisting of Ag, Au and Pt; and performing a metal-induced chemical etching for the silicon material by using an etching solution. Accordingly, a drawback that Ag nanoparticles are utilized to perform the metal-induced chemical etching in prior art is solved.
    Type: Application
    Filed: January 4, 2012
    Publication date: January 10, 2013
    Applicant: National Taiwan University of Science and Technology
    Inventors: Yung-Jr Hung, San-liang Lee, Kai-Chung Wu
  • Publication number: 20120083128
    Abstract: A method for etching high-aspect-ratio features is disclosed. The method is applicable in forming a nanoscale deep trench having a smooth and angle-adjustable sidewall. The method includes: forming a patterned photoresist layer on a surface of a silicon substrate for exposing a part of the silicon substrate; and supplying a process gas simultaneously containing sulfur hexafluoride (SF6) and fluorinated carbon composition into a chamber in which the substrate in positioned for carrying out a deep reactive ion etching operation to etch the part of the silicon substrate for forming the deep trench. The method forms a nanoscale deep trench with a high silicon-to-photoresist etching selectivity.
    Type: Application
    Filed: April 4, 2011
    Publication date: April 5, 2012
    Applicant: National Taiwan University of Science and Technology
    Inventors: Yung-jr Hung, San-liang Lee