Abstract: The present invention is a variable length decoder architecture. A bit-serial variable length decoder (VLD) receives the coded bit stream directly without buffering. The bit serial VLD determines the end of every variable length code word but does not actually decode the code words. The variable length code words are then buffered and decoded by a plurality of VLD's arranged in parallel. High throughout is achieved with a small amount of buffer capacity.

Abstract: A multiple-delay variable delay circuit uses a random access memory (RAM) array to provide adjustable delay of a block of input data, such as previously necessitated use of an extensive shift register configuration. A single RAM array, having a given capacity, is used to economically provide individual delays to a plurality of blocks of input data, with the aggregate of the individual delays not exceeding the capacity of the single RAM array. Time-shared use of a high speed RAM enables simultaneous single-port processing of data blocks, with delay control circuits providing utilization of separate portions of the RAM capacity, to provide individual delays resulting from successive read/write cycles utilizing a desired total of incremental delays. Simplified delay control circuits provide manufacturing and operating economies with single-port or multi-port RAM arrays.

Abstract: The present invention discloses an apparatus for receiving an ordered sequence of input data and for delaying the output of a delay output item by a variable-length delay-time. The apparatus includes an input port for receiving the ordered sequence of input data and the variable-length delay-time. The apparatus further includes an integrated data storage, a random access memory (RAM) for storing the ordered sequence of input data according to a storage-order corresponding to the ordered sequence of the input data. The apparatus further includes a delay output port for accessing and outputting the delay output item in the storage means according to the variable-length delay-time and the storage-order such that the delay output item is delayed by the variable-length delay-time.

Abstract: The present invention comprises a high definition television (HDTV) receiver receiving a plurality of video data for display. The HDTV receiver comprises a VLD to first decode each of the video data into a fix-length data. The HDTV receiver further comprises a plurality of data memory banks for storing in parallel the fix-length data, and a plurality of run-length decoders (RLDs) to process in parallel the fix-length video data from the memory banks.

Abstract: An HDTV decoder comprises a variable length decoder for decoding variable length code words in parallel to generate fixed length code words. A buffer for buffering the fixed length code words is connected to an output of the variable length decoder. A run length decoder is connected to an output of the buffer for run length decoding the fixed length code words. The variable length decoder has the same input and output running speed, which running speed is larger than an average speed and smaller than a burst speed at which said parallel variable length decoder would have to operate in the absence of said buffer. When the variable length decoder is capable of decoding more than one variable length code word in a cycle, the required buffer is quite small. It may be less than 1 k byte and may be on the order of 100 bytes. In this case, the variable length decoder and buffer may be incorporated in a single integrated circuit.

Abstract: A high speed variable length decoder can decode more than one code word in one cycle. A PLA used in the decoder includes extra product lines and extra output lines in order to detect and decode two successive short length code words in one cycle. When two short length code words are detected, a corresponding extra product line is activated and the two code words are decoded in the same cycle using an extra output line. For a digital video compression system, a significant speed-up in the variable length decoder can be achieved by the invention.