Patents by Inventor Yung-Liang Kuo
Yung-Liang Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230366925Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.Type: ApplicationFiled: July 27, 2023Publication date: November 16, 2023Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
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Patent number: 11754621Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.Type: GrantFiled: June 29, 2022Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
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Publication number: 20230251306Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
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Patent number: 11630149Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.Type: GrantFiled: June 21, 2021Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
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Publication number: 20220326300Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
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Patent number: 11448692Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.Type: GrantFiled: March 11, 2021Date of Patent: September 20, 2022Assignee: TAIWANN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
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Publication number: 20210311110Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
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Patent number: 11073551Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.Type: GrantFiled: July 25, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
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Publication number: 20210199710Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.Type: ApplicationFiled: March 11, 2021Publication date: July 1, 2021Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
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Publication number: 20200064396Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.Type: ApplicationFiled: July 25, 2019Publication date: February 27, 2020Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
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Patent number: 8248091Abstract: A universal system for testing different semiconductor devices provides a probe head with a probe pattern that may be used to test different test patterns formed on different semiconductor devices. Each of a plurality of bumps or pads of the test pattern contacts a corresponding probe of the probe head to enable the semiconductor device to be tested. The universal probe head may additionally or alternatively include a substrate design on the probe head that provides a pattern on the substrate of the probe head that may be used in conjunction with different patterns formed on a plurality of different printed circuit boards for testing different semiconductor devices.Type: GrantFiled: October 20, 2006Date of Patent: August 21, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsu Ming Cheng, Yung-Liang Kuo, Pi-Huang Lee, Ann Luh, Frank Hwang, Wen-Hung Wu
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Patent number: 7781235Abstract: A method of forming a semiconductor structure includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate; a plurality of through-silicon vias in the substrate; and a plurality of under bump metallurgies (UBMs) connected to the plurality of through-silicon vias, wherein the UBMs are on the first side of the stack structure. The method further includes attaching a handling wafer on the second side of the stack structure; performing a chip probing process; and removing the handling wafer from the stack structure.Type: GrantFiled: December 21, 2006Date of Patent: August 24, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Liang Luo, Yung-Liang Kuo, Hsu Ming Cheng
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Patent number: 7598523Abstract: A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second bonding pads are electrically disconnected from integrated circuit devices in the semiconductor die. A conductive feature electrically shorts the first and the second bonding pads. An additional die including an interconnect structure is bonded onto the semiconductor die. The interconnect structure includes a third and a fourth bonding pad bonded to the first and the second bonding pads, respectively. Through-wafer vias in the additional die are further connected to the third and fourth bonding pads.Type: GrantFiled: March 19, 2007Date of Patent: October 6, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Liang Luo, Yung-Liang Kuo, Hsu Ming Cheng
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Publication number: 20080272372Abstract: A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second bonding pads are electrically disconnected from integrated circuit devices in the semiconductor die. A conductive feature electrically shorts the first and the second bonding pads. An additional die including an interconnect structure is bonded onto the semiconductor die. The interconnect structure includes a third and a fourth bonding pad bonded to the first and the second bonding pads, respectively. Through-wafer vias in the additional die are further connected to the third and fourth bonding pads.Type: ApplicationFiled: March 19, 2007Publication date: November 6, 2008Inventors: Wen-Liang Luo, Yung-Liang Kuo, Hsu Ming Cheng
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Publication number: 20080153187Abstract: A method of forming a semiconductor structure includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate; a plurality of through-silicon vias in the substrate; and a plurality of under bump metallurgies (UBMs) connected to the plurality of through-silicon vias, wherein the UBMs are on the first side of the stack structure. The method further includes attaching a handling wafer on the second side of the stack structure; performing a chip probing process; and removing the handling wafer from the stack structure.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Wen-Liang Luo, Yung-Liang Kuo, Hsu Ming Cheng