Patents by Inventor YUNG-LIN TSENG

YUNG-LIN TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RESISTOR BETWEEN DUMMY FLASH STRUCTURES
    Publication number: 20240315017
    Abstract: A resistor between dummy flash structures includes a substrate. The substrate includes a resistor region and a flash region. A first dummy memory gate structure and a second dummy memory gate structure are disposed within the resistor region of the substrate. A polysilicon resistor is disposed between the first dummy memory gate structure and the second dummy memory gate structure. The polysilicon resistor contacts the first dummy memory gate structure and the second dummy memory gate structure.
    Type: Application
    Filed: April 17, 2023
    Publication date: September 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: WEICHANG LIU, Wang Xiang, CHIA CHING HSU, Yung-Lin Tseng, Shen-De Wang
  • SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    Publication number: 20240155843
    Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 9, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wang Xiang, CHIA CHING HSU, Shen-De Wang, Yung-Lin Tseng, WEICHANG LIU
  • Memory structure
    Patent number: 10692875
    Abstract: A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 23, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Wang Xiang, Chia-Ching Hsu, Chun-Sung Huang, Yung-Lin Tseng, Wei-Chang Liu, Shen-De Wang
  • MEMORY STRUCTURE
    Publication number: 20200119027
    Abstract: A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.
    Type: Application
    Filed: November 1, 2018
    Publication date: April 16, 2020
    Inventors: WANG XIANG, CHIA-CHING HSU, CHUN-SUNG HUANG, YUNG-LIN TSENG, WEI-CHANG LIU, SHEN-DE WANG