Abstract: An overhead hoist transfer apparatus includes a rail assembly including a straight rail having an empty section, and a curved rail having a curved empty section; an engine including a first LSD having first and second wheels at two sides respectively; and a second LSD having third and fourth wheels at two sides respectively; a moving carriage driven by the engine and suspended from the rail assembly; first and second guide wheels disposed on the first LSD; third and fourth guide wheels disposed on the second LSD; and two guide boards disposed above a joining point of the straight rail and the curved rail. An elevation of the guide boards is equal to that of the guide wheels. The guide board includes a straight edge and a curved edge.

Abstract: The disclosed technology provides solutions for localizing a robotic arm to facilitate entry into and cleaning of an autonomous vehicle (AV) cabin. A process of the disclosed technology can include steps for locating a door handle of an AV, actuating the door handle to open a door of the AV, and positioning a robotic arm inside a cabin of the AV. The process may further include steps for collecting image data representing the cabin using an optical sensor disposed on a distal end of the robotic arm, identifying one or more features within the cabin based, and localizing the robotic arm within the cabin of the AV. Systems and machine-readable media are also provided.

Abstract: The disclosed technology provides solutions for facilitating automated cleaning of an autonomous vehicle (AV) and in particular, for identifying objects and maintenance areas within an AV cabin. A process of the disclosed technology can include steps for collecting sensor data representing a cabin of an autonomous vehicle (AV) using an optical sensor disposed on a robotic arm, identifying one or more objects represented by the sensor data, and determining if the cabin of the AV can be cleaned using one or more tools associated with the robotic arm based on an identification of at least one of the one or more objects. Systems and machine-readable media are also provided.

Abstract: A powered industrial truck includes a lateral movement assembly including four sliding members and four pivotal members both on a wheeled carriage, four links having a first end pivotably secured to the sliding member and a second end pivotably secured to either end of the pivotal member, a motor shaft having two ends pivotably secured to the pivotal members respectively, a first electric motor on one frame member, and four mounts attached to the sliding members respectively; two lift assemblies including a second electric motor, a shaft having two ends rotatably secured to the sliding members respectively, two gear trains at the ends of the shaft respectively, a first gear connected to the second electric motor, a second gear on the shaft, and a first roller chain on the first and second gears; two electric attachments on the platform and being laterally moveable, each attachment. The mount has rollers.

Abstract: A resonant switching power converter circuit including: a switching converter, a control circuit and a pre-charging circuit; wherein the control circuit controls a first switch of the switching converter in a pre-charging mode, so as to control electrical connections between a first power and at least one of plural capacitors of the switching converter, and to control other switches of the switching converter, so as to control the pre-charging circuit to charge at least one capacitor to a predetermined voltage; wherein in a start-up mode, the plural switches control electrical connections of the capacitors according to first and second operation signals, such that after the pre-charging mode ends, the switching converter subsequently operates in the start-up mode; wherein in the start-up mode, the first and second operation signals have respective ON periods, and the time lengths of the ON periods increase gradually.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a first trench in the base and between the first fin and the second fin. The method includes forming an isolation layer over the base and in the first trench. The first fin and the second fin are partially in the isolation layer. The method includes forming a first gate stack over the first fin and the isolation layer. The method includes forming a second gate stack over the second fin and the isolation layer. The method includes removing a bottom portion of the base. The isolation layer passes through the base after the bottom portion of the base is removed.

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first source/drain structure and a second source/drain structure over and in a substrate. The method includes forming a first gate stack, a second gate stack, a third gate stack, and a fourth gate stack over the substrate. Each of the first gate stack or the second gate stack is wider than each of the third gate stack or the fourth gate stack. The method includes forming a first contact structure and a second contact structure over the first source/drain structure and the second source/drain structure respectively. A first average width of the first contact structure is substantially equal to a second average width of the second contact structure.

Abstract: A power consumption behavior analyzing device and a power consumption behavior analyzing method are provided.

Abstract: A battery pack for an information handling system includes a battery cell configured to provide current to the information handling system, and a battery management unit including an output to the information handling system. The output provides a maximum continuous current (MCC) indication and a peak power (PP) indication. The battery management unit determines an amount of current that the battery cell provides to the information handling system and determines an optimum MCC value that the battery cell can provide to the information handling system. The battery management unit further provides a first value on the PP indication, the first value being greater than the optimum MCC value, sums the amount of current provided to the information handling system that is in excess of the optimum MCC value, determines that the sum is greater than a threshold, and provides a second value on the PP indication, the second value being less than the optimum MCC value.

Abstract: A rotary seat including a base includes an outer surface, and a composite material layer attached to at least a part of the outer surface. The base also includes a recess for accommodating a turntable and including a first opening on the outer surface. The material of the composite material layer includes fibers and a resin. Therefore, the rotary seat may be more lightweight. A rotary table is also provided and includes the rotary seat, a driving device which drives the rotary seat to rotate, and a turntable which is rotatably disposed in the recess of the base.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.

Abstract: The present invention provides a resonant switched capacitor voltage converter (RSCC), which is coupled to and operates synchronously with another RSCC. The RSCC includes: plural switches, a resonant inductor, a resonant capacitor, and a control circuit. The control circuit controls the switches, so that the resonant capacitor and the resonant inductor are connected in series to each other, to perform resonant operation in a switching period, thus converting an input voltage to an output voltage. The control circuit generates a zero current signal and a first synchronization signal when a resonant inductor current flowing through the resonant inductor is zero. The control circuit turns off at least one corresponding switch according to the zero current signal. The control circuit turns on at least one corresponding switch according to the zero-current signal and a second synchronization signal, so that the RSCC operates in synchronization with at least another RSCC.

Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.

Abstract: A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures.

Abstract: A semiconductor device and method for fabricating a semiconductor device includes etch selectivity tuning to enlarge epitaxy process windows. Through modification of etching processes and careful selection of materials, improvements in semiconductor device yield and performance can be delivered. Etch selectivity is controlled by using dilute gas, using assistive etch chemicals, controlling a magnitude of bias power used in the etching process, and controlling an amount of passivation gas used in the etching process, among other approaches. A recess is formed in a dummy fin in a region of the semiconductor where epitaxial growth occurs to further enlarge the epitaxy process window.

Abstract: A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures.

Abstract: The present invention provides methods and compositions for treating advanced stage non-small cell lung cancer by cyclohexenone compounds.

Abstract: A nasogastric tube contains: a body, a plug, and a pH (potential of hydrogen) sensor. The body includes a feeding portion, a discharging portion, and a conduit. The feeding portion has a cap, and the discharging portion has multiple through orifices. The plug includes a connecting portion and a protruded portion. The protruded portion has a smooth surface. The pH sensor is injection molded to integrate into the plug, and the pH sensor includes a pH sensing element and two antennas. The pH sensing element is made of conducting material which is configured to produce different voltage response with a pH ion concentration in gastric juice. The pH value of the gastric juice measured by the pH sensing element is wirelessly send by the two antennas to a reader, and the pH value of the gastric juice measured is displayed on the reader.

Abstract: A semiconductor device and method for fabricating a semiconductor device includes etch selectivity tuning to enlarge epitaxy process windows. Through modification of etching processes and careful selection of materials, improvements in semiconductor device yield and performance can be delivered. Etch selectivity is controlled by using dilute gas, using assistive etch chemicals, controlling a magnitude of bias power used in the etching process, and controlling an amount of passivation gas used in the etching process, among other approaches. A recess is formed in a dummy fin in a region of the semiconductor where epitaxial growth occurs to further enlarge the epitaxy process window.