Patents by Inventor Yung Long Hung
Yung Long Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240379444Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.Type: ApplicationFiled: July 14, 2024Publication date: November 14, 2024Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
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Patent number: 12080604Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.Type: GrantFiled: July 31, 2023Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Wei Lee, Chien-Yuan Chen, Jo-Chun Hung, Yung-Hsiang Chan, Yu-Kuan Lin, Lien-Jung Hung
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Patent number: 7504183Abstract: A phase-shifting mask suited for equal line/space, small pitched, dense line pattern is disclosed. The phase-shifting mask includes a transparent substrate, a partially shielded mesa line pattern of first phase formed on the substrate, and a clear recessed line pattern of second phase etched into the substrate and is disposed right next to the partially shielded mesa line pattern. The partially shielded mesa line pattern has a plurality of alternating 5%-10% transmittance light-shielding regions and clear regions of the first phase. The partially shielded mesa line pattern and the clear recessed line pattern have the same line width. The light that passes through the clear regions of the first phase and the light that passes through the clear recessed line pattern of second phase have a phase difference of 180 degree.Type: GrantFiled: June 24, 2005Date of Patent: March 17, 2009Assignee: Nanya Technology Corp.Inventors: Yung-Long Hung, Yuan-Hsun Wu, Chia-Tsung Hung
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Patent number: 7504184Abstract: A phase-shifting mask suited for equal line/space, small pitched, dense line pattern is disclosed. The phase-shifting mask includes a transparent substrate, a partially shielded mesa line pattern of first phase formed on the substrate, and a 100% clear recessed line pattern of second phase etched into the substrate and is disposed right next to the partially shielded mesa line pattern. The partially shielded mesa line pattern has a plurality of alternating 45-degree, oblique areas and 100% transmittance clear regions of the first phase. The partially shielded mesa line pattern and the clear recessed line pattern have the same line width. The light that passes through the clear regions of the first phase and the light that passes through the clear recessed line pattern of second phase have a phase difference of 180 degree.Type: GrantFiled: June 27, 2005Date of Patent: March 17, 2009Assignee: Nanya Technology Corp.Inventors: Yung-Long Hung, Yuan-Hsun Wu
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Publication number: 20070054201Abstract: A phase shifting mask suited for equal line/space, small pitched, dense line pattern is disclosed. The phase shifting mask includes a transparent substrate, a partially shielded mesa line pattern of first phase formed on the substrate, and a transparent recessed line pattern of second phase etched into the substrate and is disposed right next to the partially shielded mesa line pattern. The partially shielded mesa line pattern has a plurality of alternating opaque regions and transparent regions of the first phase. The partially shielded mesa line pattern and the clear recessed line pattern have the same line width. The light that passes through the transparent regions of the first phase and the light that passes through the transparent recessed line pattern of second phase have a phase difference of 180 degree.Type: ApplicationFiled: August 7, 2006Publication date: March 8, 2007Inventors: Yung-Long Hung, Yuan-Hsun WU, Chia-Tsung Hung
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Publication number: 20060240333Abstract: A phase-shifting mask suited for equal line/space, small pitched, dense line pattern is disclosed. The phase-shifting mask includes a transparent substrate, a partially shielded mesa line pattern of first phase formed on the substrate, and a 100% clear recessed line pattern of second phase etched into the substrate and is disposed right next to the partially shielded mesa line pattern. The partially shielded mesa line pattern has a plurality of alternating 45-degree, oblique areas and 100% transmittance clear regions of the first phase. The partially shielded mesa line pattern and the clear recessed line pattern have the same line width. The light that passes through the clear regions of the first phase and the light that passes through the clear recessed line pattern of second phase have a phase difference of 180 degree.Type: ApplicationFiled: June 27, 2005Publication date: October 26, 2006Inventors: Yung-Long Hung, Yuan-Hsun WU
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Publication number: 20060240332Abstract: A phase-shifting mask suited for equal line/space, small pitched, dense line pattern is disclosed. The phase-shifting mask includes a transparent substrate, a partially shielded mesa line pattern of first phase formed on the substrate, and a clear recessed line pattern of second phase etched into the substrate and is disposed right next to the partially shielded mesa line pattern. The partially shielded mesa line pattern has a plurality of alternating 5%-10% transmittance light-shielding regions and clear regions of the first phase. The partially shielded mesa line pattern and the clear recessed line pattern have the same line width. The light that passes through the clear regions of the first phase and the light that passes through the clear recessed line pattern of second phase have a phase difference of 180 degree.Type: ApplicationFiled: June 24, 2005Publication date: October 26, 2006Inventors: Yung-Long Hung, Yuan-Hsun WU, Chia-Tsung Hung
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Patent number: 7052810Abstract: A method of correcting optical proximity effect of contact holes. Corresponding relations between mask critical dimensions (mCDs) and photoresist critical dimensions (pCDs) for each pitch (d) are formed. Correction of each mCD for each combination of pCDs and pitches is determined based on the corresponding relations. The correction is used first to correct each contact hole of a processing mask pattern. The first corrected contact hole of the processing mask pattern is corrected again to a square having the same area as the first corrected contact hole and the same center as the uncorrected contact hole.Type: GrantFiled: June 18, 2004Date of Patent: May 30, 2006Assignee: Nanya Technology CorporationInventors: Tsan Lu, Wen-Bin Wu, Yung-Long Hung, Cheng-Kung Lu
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Patent number: 6998226Abstract: A method of forming a patterned photoresist layer. First, an anti-reflection coating layer is formed on a substrate. Next, a first bake is performed. A photoresist layer is then formed on the anti-reflection coating layer. Exposure is performed. A second bake is performed, wherein the temperature difference between the first bake and the second bake is about 35 ° C.˜55 ° C. Finally, development is performed. The patterned photoresist layer features have perfect profiles in accordance with this invention.Type: GrantFiled: July 10, 2002Date of Patent: February 14, 2006Assignee: Nanya Technology CorporationInventors: Yuan-Hsun Wu, Wen-Bin Wu, Yung Long Hung, Ya Chih Wang
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Publication number: 20050003284Abstract: A method of correcting optical proximity effect of contact holes. Corresponding relations between mask critical dimensions (mCDs) and photoresist critical dimensions (pCDs) for each pitch (d) are formed. Correction of each mCD for each combination of pCDs and pitches is determined based on the corresponding relations. The correction is used first to correct each contact hole of a processing mask pattern. The first corrected contact hole of the processing mask pattern is corrected again to a square having the same area as the first corrected contact hole and the same center as the uncorrected contact hole.Type: ApplicationFiled: June 18, 2004Publication date: January 6, 2005Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Tsan Lu, Wen-Bin Wu, Yung-Long Hung, Cheng-Kung Lu
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Publication number: 20030180666Abstract: A method of forming a patterned photoresist layer. First, an anti-reflection coating layer is formed on a substrate. Next, a first bake is performed. A photoresist layer is then formed on the anti-reflection coating layer. Exposure is performed. A second bake is performed, wherein the temperature difference between the first bake and the second bake is about 35° C.˜55 ° C. Finally, development is performed. The patterned photoresist layer features have perfect profiles in accordance with this invention.Type: ApplicationFiled: July 10, 2002Publication date: September 25, 2003Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Yuan-Hsun Wu, Wen-Bin Wu, Yung Long Hung, Ya Chih Wang