Patents by Inventor Yung-Lung Chen

Yung-Lung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145431
    Abstract: A method includes: attaching a first die and a second die to a substrate, the first die comprising a conductive via; forming a die spacer between the first die and the second die; thinning the first die and the second die, wherein after thinning the first die and the second die, the die spacer protrudes a first height above an upper surface of the first die; depositing an insulating layer over the first die and the second die; planarizing the insulating layer, wherein after planarizing, the insulating layer has a first thickness above the first die and a second thickness above the die spacer; attaching a third die and a fourth die to the first die and the second die; and attaching a support substrate to the third die and the fourth die.
    Type: Application
    Filed: January 6, 2023
    Publication date: May 2, 2024
    Inventors: Yung-Lung Chen, Ming-Yun Liao, Yi-Hsiu Chen, Wen-Chih Chiou
  • Patent number: 11973148
    Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Ying Wu, Yung-Hsiang Chen, Yu-Lung Yeh, Yen-Hsiu Chen, Wei-Liang Chen, Ying-Tsang Ho
  • Patent number: 11951569
    Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Ming Wu, Yung-Lung Lin, Hau-Yi Hsiao, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Patent number: 11946569
    Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Chung-Wei Kao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
  • Patent number: 10879214
    Abstract: Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 ?m per 1 mm range. A method of manufacturing the die stack structure is also provided.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Wen-Chih Chiou, Yung-Lung Chen
  • Publication number: 20190131276
    Abstract: Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 ?m per 1 mm range. A method of manufacturing the die stack structure is also provided.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiu Chen, Wen-Chih Chiou, Yung-Lung Chen
  • Patent number: 9303117
    Abstract: A series of ladder-type multifused arenes (hexacyclic, heptacyclic and nonacyclic units) and the synthesizing methods thereof are provided. The ladder-type multifused arenes are copolymerized with various electron-deficient acceptor units to afford various p-type low-band gap conjugated copolymers.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 5, 2016
    Assignee: National Chiao Tung University
    Inventors: Chain-Shu Hsu, Yen-Ju Cheng, Jhong-Sian Wu, Chiu-Hsiang Chen, Huan-Hsuan Chang, Yung-Lung Chen, Sheng-Wen Cheng
  • Publication number: 20150299382
    Abstract: A series of ladder-type multifused arenes (hexacyclic, heptacyclic and nonacyclic units) and the synthesizing methods thereof are provided. The ladder-type multifused arenes are copolymerized with various electron-deficient acceptor units to afford various p-type low-band gap conjugated copolymers.
    Type: Application
    Filed: June 29, 2015
    Publication date: October 22, 2015
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chain-Shu HSU, Yen-Ju Cheng, Jhong-Sian Wu, Chiu--Hsiang Chen, Huan-Hsuan Chang, Yung-Lung Chen, Sheng-Wen Cheng
  • Patent number: 9096716
    Abstract: A series of ladder-type multifused arenes (hexacyclic, heptacyclic and nonacyclic units) and the synthesizing methods thereof are provided. The ladder-type multifused arenes are copolymerized with various electron-deficient acceptor units to afford various p-type low-band gap conjugated copolymers.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: August 4, 2015
    Assignee: National Chiao Tung University
    Inventors: Chain-Shu Hsu, Yen-Ju Cheng, Jhong-Sian Wu, Chiu-Hsiang Chen, Huan-Hsuan Chang, Yung-Lung Chen, Sheng-Wen Cheng
  • Publication number: 20140163191
    Abstract: A series of ladder-type multifused arenes (hexacyclic, heptacyclic and nonacyclic units) and the synthesizing methods thereof are provided. The ladder-type multifused arenes are copolymerized with various electron-deficient acceptor units to afford various p-type low-band gap conjugated copolymers.
    Type: Application
    Filed: November 27, 2013
    Publication date: June 12, 2014
    Applicant: Nation Chiao Tung University
    Inventors: Chian-Shu Hsu, Yen-Ju Cheng, Jhong-Sian Wu, Chiu-Hsiang Chen, Huan-Hsuan Chang, Yung-Lung Chen, Sheng-Wen Cheng
  • Patent number: 8623993
    Abstract: A series of ladder-type multifused arenes (hexacyclic, heptacyclic and nonacyclic units) and the synthesizing methods thereof are provided. The ladder-type multifused arenes are copolymerized with various electron-deficient acceptor units to afford various p-type low-band gap conjugated copolymers.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: January 7, 2014
    Assignee: National Chaio Tung University
    Inventors: Chian-Shu Hsu, Yen-Ju Cheng, Jhong-Sian Wu, Chiu-Hsiang Chen, Huan-Hsuan Chang, Yung-Lung Chen, Sheng-Wen Cheng
  • Publication number: 20130237676
    Abstract: A series of ladder-type multifused arenes (hexacyclic, heptacyclic and nonacyclic units) and the synthesizing methods thereof are provided. The ladder-type multifused arenes are copolymerized with various electron-deficient acceptor units to afford various p-type low-band gap conjugated copolymers.
    Type: Application
    Filed: June 25, 2012
    Publication date: September 12, 2013
    Applicant: NATION CHIAO TUNG UNIVERSITY
    Inventors: Yen-Ju Cheng, Jhong-Sian Wu, Chiu-Hsiang Chen, Huan-Hsuan Chang, Yung-Lung Chen, Sheng-Wen Cheng
  • Patent number: 8330746
    Abstract: Addressing method for multiple chips is provided. Each chip includes an input enable terminal, an output enable terminal, a data input terminal, and a clock terminal. The output enable terminal of a previous stage is connected to the input enable terminal of a next stage. The method includes setting an initial address to an address of each chip via a system; setting a state of each chip to a disable state; enabling the state of a first-one chip among the chips to an enable state, and setting the first chip as a previous-stage chip; updating the address of the previous-stage chip; enabling a next-stage chip connected after the previous-stage chip, in which the system controls the output enable terminal of the previous-stage chip to output an enable signal to enable the next-stage chip, according to the address of the previous-stage chip; and the updating the address of the next-stage chip.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: December 11, 2012
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jen-Ta Yang, Yung-Lung Chen
  • Publication number: 20110018888
    Abstract: Addressing method for multiple chips is provided. Each chip includes an input enable terminal, an output enable terminal, a data input terminal, and a clock terminal. The output enable terminal of a previous stage is connected to the input enable terminal of a next stage. The method includes setting an initial address to an address of each chip via a system; setting a state of each chip to a disable state; enabling the state of a first-one chip among the chips to an enable state, and setting the first chip as a previous-stage chip; updating the address of the previous-stage chip; enabling a next-stage chip connected after the previous-stage chip, in which the system controls the output enable terminal of the previous-stage chip to output an enable signal to enable the next-stage chip, according to the address of the previous-stage chip; and the updating the address of the next-stage chip.
    Type: Application
    Filed: September 16, 2009
    Publication date: January 27, 2011
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventors: Jen-Ta Yang, Yung-Lung Chen
  • Patent number: 7493485
    Abstract: A structure of embedded memory unit with loader comprises a main memory area and an information area as a part of the main memory area. A plurality of loader-program parts is dispersedly stored in different addresses of the main memory area, wherein the loader-program parts are combined to form a complete loader. A loader mapping area is used to store the loader-program during the boot stage. When the boot sequence starts, the original information stored in the loader mapping area is temporarily backup to a temporary space; and the released space is used to store the loader-program. After the boot sequence is completed, the original information is moved back to the original location.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: February 17, 2009
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yung-Lung Chen, Chia-Jung Yang
  • Patent number: 7386065
    Abstract: A voltage controlled oscillator (VCO), suitable for use in a frequency shift keying (FSK) system. The VCO device comprises a switching varactor unit, having a first terminal and a second terminal, wherein the switching varactor unit produces a capacitance, according to a frequency-selection voltage. A VCO core has a first output terminal, a second output terminal complementary to the first output terminal, and an input terminal. Wherein, the switching varactor unit is coupled in parallel with the VCO core at the first output terminal and the second output terminal to produce a capacitance effect with respect to the capacitance, so as to adjust a frequency constant ?{square root over (LC)} of the VCO core.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: June 10, 2008
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yih-Min Tu, Yung-Lung Chen, Yuan-Tung Peng, Fan-Chung Lee
  • Publication number: 20070270662
    Abstract: An apparatus for monitoring end user's health status via a network comprises at least one system server or a personal server connected to a plurality of monitoring devices and a plurality of medical organization servers. The monitoring devices, the system server or the personal sever, and the medical organization servers are connected by wireless transmission and network. When an alarm message is sent out from the end user, the personal server will send this information to predetermined telephone or to the medical organization server automatically, the telephone can be family or relative's mobile phone, or the telephone of a medical or rescue organization. Therefore, the end user can get an immediate treatment.
    Type: Application
    Filed: May 19, 2006
    Publication date: November 22, 2007
    Inventor: Yung-Lung Chen
  • Patent number: 7269233
    Abstract: An algorithm for bit synchronization in a frequency shift keying (FSK) receiver. In the algorithm, a training sequence is received from a transmitter. The training sequence has a plurality of bits. A starting point of a next bit received by the FSK receiver after the training sequence is determined according to peak values of the bits of the training sequence.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: September 11, 2007
    Assignee: Novatek Microelectronics Corp.
    Inventors: David Shiung, Yung-Lung Chen
  • Patent number: 7145967
    Abstract: A frequency shift key decoding apparatus, having a frequency divider, a signal frequency splitter, and a demodulator. The signal frequency splitter has a frequency synthesizer, (n?1) first mixers, n second mixers, and n filters, where n is an integer equal to or larger than 2. The present invention can be applied to a multi-function wireless receiver that supports multiple peripherals. Since a plurality of local carrier signals is generated by only (n?1) mixers, the frequency of the local carrier signals can be randomly changed. As the mixers occupy a very small area of the integrated circuit chip, the fabrication cost is low. Further, since the mixers are easily implemented using a digital circuit, the frequency shift key decoding apparatus, and even the whole wireless receiver can be implemented in a single chip.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: December 5, 2006
    Assignee: Novatek Microelectronics Corp.
    Inventor: Yung-Lung Chen
  • Publication number: 20060253695
    Abstract: A structure of embedded memory unit with loader comprises a main memory area and an information area as a part of the main memory area. A plurality of loader-program parts is dispersedly stored in different addresses of the main memory area, wherein the loader-program parts are combined to form a complete loader. A loader mapping area is used to store the loader-program during the boot stage. When the boot sequence starts, the original information stored in the loader mapping area is temporarily backup to a temporary space; and the released space is used to store the loader-program. After the boot sequence is completed, the original information is moved back to the original location.
    Type: Application
    Filed: July 12, 2005
    Publication date: November 9, 2006
    Inventors: Yung-Lung Chen, Chia-Jung Yang