Abstract: A projector includes a light source, a fan and a guiding passage. The fan is disposed beside a first side of the light source. The guiding passage has a guiding inlet and a guiding outlet. The guiding passage extends from a section near the fan to a section near a second side of the light source. The fan is capable of generating a first airflow and a second airflow. The first airflow is capable of being mixed with the second airflow near the second side of the light source. The second airflow is guided by the guiding passage so that the second airflow is mixed with the first airflow near the second side of the light source.

Abstract: The invention provides a contact pad supporting structure. The contact pad supporting structure includes an underlying first conductive plate and an overlying second conductive plate, wherein the first and second conductive plates are separated by a first dielectric layer. A plurality of circular ring-shaped via plug groups comprising a plurality of circular ring-shaped via plugs is through the first dielectric layer, electrically connecting to the first and second conductive plates. All of the circular ring-shaped via plugs of each of the circular ring-shaped via plug groups are disorderly arranged.

Abstract: A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.

Abstract: A fuse circuit comprising one or more one-time programmable electrical fuses; one or more unidirectional conductive devices each coupled to one of the fuses; a programming device coupled to the unidirectional conductive devices; and a selection module coupled to the electrical fuses for selecting a predetermined electrical fuse, wherein upon a selection by the selection module, a programming current is introduced through at least one selected electrical fuse, wherein the selection module is an N-to-one multiplexer selecting one of the N number of electrical fuses to be programmed, and the unidirectional conductive devices not coupled to the selected electrical fuse to prevent the programming current from interfering with the remaining electrical fuses.

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.

Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.

Abstract: A manufacturing method of a filter is provided. The manufacturing method includes steps as follows. First, a substrate is provided and a black matrix is formed on the substrate. The black matrix has a number of openings arranged in array. Next, a filter material is individually formed in the openings by inkjet printing or other methods, and the filter material includes a solvent and a dye mixed with the solvent. Thereafter, a thermal treatment is performed and an evaporation rate of the solvent during the thermal treatment is reduced, so as to cure the filter material. As the evaporation rate of the solvent is relatively slow, the filter material is still flowable during the thermal treatment. Hence, the cured filter material has a flat surface. The filter fabricated by the above manufacturing method has an even hue and a well flattened surface.

Abstract: A manufacturing method of a color filter including following steps is provided. First, a partition is formed on a substrate to form a plurality of pixel regions on the substrate. Next, a color pigment is provided along a continuous pigment-providing route, so as to form the color pigment on a sequence of pixel regions among the plurality of pixel regions and the partition. The method mentioned above can prevent the unfilled phenomenon of the pigment around the corners of the pixel region. Besides, a liquid crystal display panel having the color filter is also provided.

Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

Abstract: A fuse circuit comprising one or more one-time programmable electrical fuses; one or more unidirectional conductive devices each coupled to one of the fuses; a programming device coupled to the unidirectional conductive devices; and a selection module coupled to the electrical fuses for selecting a predetermined electrical fuse, wherein upon a selection by the selection module, a programming current is introduced through at least one selected electrical fuse, wherein the selection module is an N-to-one multiplexer selecting one of the N number of electrical fuses to be programmed, and the unidirectional conductive devices not coupled to the selected electrical fuse to prevent the programming current from interfering with the remaining electrical fuses.

Abstract: A color filter including a substrate, a bank and a plurality of color filter films is provided. The bank is disposed on the substrate and has many openings. The bank has both a bottom surface contacting the substrate and a top surface exceeding the bottom surface. An outline of the bottom surface does not exceed that of the top surface. Besides, the color filter films are disposed on the substrate exposed by the openings, respectively, and each of the color filter films has a curved top surface. In the above-mentioned color filter, wetability between the bank and the color filter films is favorable.

Abstract: A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.

Abstract: The disclosure generally relates to a method and apparatus for a high efficiency redundancy scheme for a memory system. In one embodiment, the disclosure relates to a memory circuit having: a memory array defined by a plurality of memory cells arranged in one or more columns and one or more rows, each memory cell communicating with one of a pair of complementary bit-lines and with a word-line; a plurality of IO circuits, each IO circuit associated with one of the plurality of memory cell columns; a plurality of redundant bit-lines, each redundant bit line communicating with a redundant bit cell; a first circuit for detecting a defective memory cell in said memory circuit; a second circuit for selecting one of the plurality of redundant bit-lines for switching from the failed memory cell to the redundant memory cell; and a third circuit for directing a word-line pulse of said defective memory cell to said selected redundant memory cell.

Abstract: A memory includes a plurality of cells arranged in a matrix having a plurality of rows and a plurality of columns, wherein each cell is capable of storing a bit. Each cell is coupled between a first power supply node that receives a power supply voltage and a second power supply node that receives a second voltage. A plurality of word lines are associated with the memory cells and supplied by a third voltage in read or write operation. The third voltage is a suppressed power supply voltage. The second voltage is negative in read operation and positive in write operation.

Abstract: A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a power node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device, a second terminal coupled to a control signal, a third terminal coupled to a first storage node of at least one tracking cell, a fourth terminal coupled to a second storage node of the tracking cell, and a fifth terminal coupled to the power node of the integrated circuit module, for controlling the switch device to pass the supply voltage to the power node with or without a substantial voltage drop depending on an operation mode of the integrated circuit module.

Abstract: A writing dynamic power control circuit is disclosed, which comprises a BL and its complementary BLB, at least one memory cell coupled to both the BL and BLB, a first NMOS transistor having a source, a drain and a gate coupled to the BL, the Vss and a first data signal, respectively, a second NMOS transistor having a source, a drain and a gate coupled to the BLB, the Vss and a second data signal, respectively, wherein the second data signal is complementary to the first data signal, a first PMOS transistor having a source, a drain and a gate coupled to a high voltage power supply (CVDD) node, the BLB and the BL, respectively, and a second PMOS transistor having a source, a drain and a gate coupled to the CVDD node, the BL and the BLB, respectively.

Abstract: A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.

Abstract: A system for generating a pulse signal in response to a clock signal includes a latch module for generating a latched output in response to a leading edge of the clock signal. A delay module is coupled to the latch module for delaying the latched output. A first logic device having a first input terminal coupled to the latch module and a second input terminal is coupled to the delay module for generating the pulse signal, which has a pulse width determined by a delay time of the latched output passing through the delay module. The pulse signal is coupled to the latch module for resetting the latch module when the pulse signal is not asserted.

Abstract: An integrated circuit for programming an electrical fuse includes a first programming device coupled to the electrical fuse for selectively providing the same with a first programming current, and a second programming device coupled to the electrical fuse for selectively providing the same with a second programming current. A detection module is coupled to the electrical fuse for generating an output indicating a resistance level of the electrical fuse, wherein the resistance level has three or more predetermined states, which are provided by selectively programming the electrical fuse with the first or second programming current.