Patents by Inventor Yung-Min Cheng

Yung-Min Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6787375
    Abstract: Within a method for electrical testing a series of microelectronic fabrication die fabricated within a microelectronic fabrication substrate, there is first electrically tested the series of microelectronic fabrication die to determine at least one sub-series of electrically unacceptable microelectronic fabrication die. Similarly, there is also determined whether the microelectronic fabrication substrate may be reworked. Finally, there is also electrically retested only the at least one sub-series of electrically unacceptable microelectronic fabrication die, and only if the microelectronic substrate may be reworked. The method provides for enhanced efficiency when electrically testing the series of microelectronic fabrication die.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: September 7, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yung-Min Cheng, Yao-Tung Liu, Chun-Tsung Yang, Juei-Feng Hsu
  • Patent number: 6724211
    Abstract: A system for monitoring semiconductor testing tools comprises a tester testing a semiconductor device, whereby a test result is derived, a storage device storing a logic function corresponding to the semiconductor device, and a processor receiving the test result and the logic function from the tester and storage device respectively, and applying the logic function to the test result for validation.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: April 20, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., LTD
    Inventors: Shun-An Chen, Li-Chung Lin, Yao-Tung Liu, Yung-Min Cheng, Ming-Hui Lin, Hsin-Hom Chen, Chun-Sheng Wang
  • Publication number: 20030211639
    Abstract: Within a method for electrical testing a series of microelectronic fabrication die fabricated within a microelectronic fabrication substrate, there is first electrically tested the series of microelectronic fabrication die to determine at least one sub-series of electrically unacceptable microelectronic fabrication die. Similarly, there is also determined whether the microelectronic fabrication substrate may be reworked. Finally, there is also electrically retested only the at least one sub-series of electrically unacceptable microelectronic fabrication die, and only if the microelectronic substrate may be reworked. The method provides for enhanced efficiency when electrically testing the series of microelectronic fabrication die.
    Type: Application
    Filed: May 13, 2002
    Publication date: November 13, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.
    Inventors: Yung-Min Cheng, Yao-Tung Liu, Chun-Tsung Yang, Juei-Feng Hsu
  • Patent number: 6590408
    Abstract: Within both an electrical test apparatus for electrically testing a substrate, and a method for electrically testing the substrate while employing the electrical test apparatus, there is provided for an automatic selection of an electrical test program, absent operator intervention, once having identified a substrate. Due to the absence of operator intervention, the substrate is more accurately electrically tested.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: July 8, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Min Cheng, Chun-Sheng Wang, Ming-Hui Lin, Sheng-Guei Chang, Juei-Feng Hsu
  • Publication number: 20020158624
    Abstract: A system for monitoring semiconductor testing tools comprises a tester testing a semiconductor device, whereby a test result is derived, a storage device storing a logic function corresponding to the semiconductor device, and a processor receiving the test result and the logic function from the tester and storage device respectively, and applying the logic function to the test result for validation.
    Type: Application
    Filed: September 12, 2001
    Publication date: October 31, 2002
    Inventors: Shun-An Chen, Li-Chung Lin, Yao-Tung Liu, Yung-Min Cheng, Ming-Hui Lin, Hsin-Hom Chen, Chun-Sheng Wang