Patents by Inventor Yung-Nien Koh

Yung-Nien Koh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11443185
    Abstract: A memory chip capable of performing artificial intelligence operation and an operation method thereof are provided. The memory chip includes a memory array, a memory controller, and an artificial intelligence engine. The memory array includes a plurality of memory areas. The memory areas are configured to store digitized input data and weight data. The memory controller is coupled to the memory array via a bus dedicated to the artificial intelligence engine. The artificial intelligence engine accesses the memory array via the memory controller and the bus to obtain the digitized input data and the weight data. The artificial intelligence engine performs a neural network operation based on the digitized input data and the weight data.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 13, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Frank Chong-Jen Huang, Yung-Nien Koh
  • Patent number: 10990524
    Abstract: A memory with a processing in memory architecture and an operating method thereof are provided. The memory includes a memory array, a mode register, an artificial intelligence core, and a memory interface. The memory array includes a plurality of memory regions. The mode register stores a plurality of memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to a special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory regions are respectively selectively assigned to the special function processing core or the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core respectively access different memory regions in the memory array according to the plurality of memory mode settings.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 27, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Frank Chong-Jen Huang, Yung-Nien Koh
  • Publication number: 20200117989
    Abstract: A memory chip capable of performing artificial intelligence operation and an operation method thereof are provided. The memory chip includes a memory array, a memory controller, and an artificial intelligence engine. The memory array includes a plurality of memory areas. The memory areas are configured to store digitized input data and weight data. The memory controller is coupled to the memory array via a bus dedicated to the artificial intelligence engine. The artificial intelligence engine accesses the memory array via the memory controller and the bus to obtain the digitized input data and the weight data. The artificial intelligence engine performs a neural network operation based on the digitized input data and the weight data.
    Type: Application
    Filed: August 22, 2019
    Publication date: April 16, 2020
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Frank Chong-Jen Huang, Yung-Nien Koh
  • Publication number: 20200117597
    Abstract: A memory with a processing in memory architecture and an operating method thereof are provided. The memory includes a memory array, a mode register, an artificial intelligence core, and a memory interface. The memory array includes a plurality of memory regions. The mode register stores a plurality of memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to a special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory regions are respectively selectively assigned to the special function processing core or the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core respectively access different memory regions in the memory array according to the plurality of memory mode settings.
    Type: Application
    Filed: September 9, 2019
    Publication date: April 16, 2020
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Frank Chong-Jen Huang, Yung-Nien Koh