Abstract: A semiconductor device and a method for manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip area in which metal wiring layers are formed, forming a dielectric film, forming a conductive film on the dielectric film in a chip area and an alignment mark on the dielectric film in a scribe lane, forming passivation films, exposing the conductive film by removing the passivation films in a bonding pad portion in a chip area, forming another conductive film in the bonding pad portion to electrically connect with the conductive film, forming another passivation film, and selectively removing the passivation films.

Abstract: An image sensor including a substrate and an interlayer dielectric layer divided into a pixel region and a logic pad region. An image sensor may include at least one of the following: a color filter, an over coating layer, and a micro lens sequentially formed over the interlayer dielectric layer in the pixel region; a top conductive layer formed over the interlayer dielectric layer of the logic pad region; an etch stop layer formed over the interlayer dielectric layer in the logic pad region and on the sides and a portion of an upper surface of a top conductive layer; and a first and second protective layers sequentially formed over the etch stop layer.

Abstract: A semiconductor device and a method for manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip area in which metal wiring layers are formed, forming a dielectric film, forming a conductive film on the dielectric film in a chip area and an alignment mark on the dielectric film in a scribe lane, forming passivation films, exposing the conductive film by removing the passivation films in a bonding pad portion in a chip area, forming another conductive film in the bonding pad portion to electrically connect with the conductive film, forming another passivation film, and selectively removing the passivation films.

Abstract: A semiconductor device and a method manufacturing the same prevents copper from being exposed to a surface of a passivation film after a copper metal line formation, to avoid contamination of processing equipment and the process environment. The method includes providing a substrate with a scribe lane and a chip area in which metal wiring layers are formed, forming a dielectric film, forming a conductive film on the dielectric film in a chip area and an alignment mark on the dielectric film in a scribe lane, forming passivation films, exposing the conductive film by removing the passivation films in a bonding pad portion in a chip area, forming another conductive film in the bonding pad portion to electrically connect with the conductive film, forming another passivation film, and selectively removing the passivation films.

Abstract: An image sensor is provided. The image sensor includes a first passivation layer, a color filter layer, microlenses, an uppermost conducting layer, a second passivation layer, and a third passivation layer. The first passivation layer is formed on a substrate including a predetermined pixel portion and a logic pad portion. The color filter layer and the microlenses are formed on a portion of the first passivation layer corresponding to the pixel portion. The uppermost conducting layer is formed in a portion of the first passivation layer that corresponds to the logic pad portion. The second passivation layer is formed on the first passivation layer corresponding to the logic pad portion to expose a portion of the uppermost conducting layer. The third passivation layer is formed on the second passivation layer to expose the uppermost conducting layer.

Abstract: An image sensor including a substrate and an interlayer dielectric layer divided into a pixel region and a logic pad region. An image sensor may include at least one of the following: a color filter, an over coating layer, and a micro lens sequentially formed over the interlayer dielectric layer in the pixel region; a top conductive layer formed over the interlayer dielectric layer of the logic pad region; an etch stop layer formed over the interlayer dielectric layer in the logic pad region and on the sides and a portion of an upper surface of a top conductive layer; and a first and second protective layers sequentially formed over the etch stop layer.

Abstract: An overlay key for a semiconductor device is provided. The semiconductor device can include a first insulating layer having a trench serving as an outer key; and a metal layer formed on the first insulating layer including in the trench of the outer key. Here, an inner key region of the metal layer is etched. The metal layer formed in the trench of the outer key can be formed on a residual first metal remaining, for example, from a via plug formation process to inhibit contact between the remaining first metal in the trench of the outer key and a second insulating layer formed on the metal layer.

Abstract: A method for forming a Metal-Insulator-Metal capacitor of a semiconductor device includes forming an insulation layer, a lower conductive layer, a dielectric layer and an upper conductive layer on a semiconductor substrate; forming, on the upper conductive layer, a protective insulation layer wherein an etching selectivity of the lower conductive layer to the protective insulation layer is high, patterning the upper conductive layer to form an upper electrode, patterning the lower conductive layer to form a lower electrode, depositing and planarizing an insulation layer, forming a via contact, and forming a metal wiring layer. Therefore, a process margin in the follow-up etching process is increased although the photosensitive film is reduced in its thickness.

Abstract: A method of fabricating an MIM capacitor is provided, by which higher capacitance can be secured per unit volume or area by forming a dual-stack type capacitor to increase an effective area of the capacitor. The method includes patterning a first metal layer, forming a planarized second insulating layer having a trench exposing a portion of the patterned first metal layer, forming a second metal layer within the trench, forming a first dielectric layer on the second metal layer, forming first via holes exposing the patterned first metal layer, forming first plugs filling the trench and first via holes, forming a third metal layer thereover, forming a second dielectric layer on the third metal layer, forming a patterned fourth metal layer on the second dielectric layer, patterning the second dielectric layer and the third metal layer, forming a planarized third insulating layer having second via holes therein, and forming a patterned fifth metal layer on the third insulating layer.

Abstract: A semiconductor device and fabricating method are provided, by which device drivability can be increased by forming second LDD regions after isolating first LDD regions from source/drain regions to prevent heavily doped impurities therein from diffusing into the first LDD regions and to provide stepped densities within the LDD regions. The method includes the steps of stacking oxide and conductive layers on a semiconductor substrate, forming a gate electrode by patterning the conductive layer, etching the exposed substrate to a first depth, forming a first LDD region in the etched substrate, forming a spacer on a sidewall of the gate electrode, forming a source/drain region in the substrate having the spacer, etching the substrate having the source/drain region to a second depth, and forming a second LDD region between the first LDD region and the source/drain region of the etched substrate.