Patents by Inventor Yung-Ping Chiang

Yung-Ping Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11335666
    Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20220013494
    Abstract: A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20210351126
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 11127708
    Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20210265289
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping CHIANG, Yi-Che CHIANG, Nien-Fang WU, Min-Chien HSIAO, Chao-Wen SHIH, Shou-Zen CHANG, Chung-Shi LIU, Chen-Hua YU
  • Publication number: 20210257717
    Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.
    Type: Application
    Filed: April 12, 2021
    Publication date: August 19, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 11075159
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 11004809
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Yi-Che Chiang, Nien-Fang Wu, Min-Chien Hsiao, Chao-Wen Shih, Shou-Zen Chang, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10978782
    Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 10937719
    Abstract: A package structure comprising a die, a first molding compound encapsulating the die, an antenna structure and a reflector pattern disposed above the die is provided. Through vias penetrating through the first molding compound are disposed around the die. The reflector pattern is disposed on the die and the through vias. The antenna structure is disposed on the reflector pattern and electrically connected with the reflector pattern and the die. The antenna structure is wrapped by a second molding compound disposed on the reflector pattern.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Min-Chien Hsiao, Nien-Fang Wu, Shou-Zen Chang, Yi-Che Chiang
  • Patent number: 10879170
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, a molding compound, a polymer layer, a conductive trace, a conductive via and an inductor. The semiconductor die is laterally surrounded by the molding compound. The polymer layer covers the semiconductor die and the molding compound. The conductive trace, the conductive via and the inductor are embedded in the polymer layer. The conductive via extends from a top surface of the conductive trace to a top surface of the polymer layer. The inductor has a body portion extending horizontally and a protruding portion protruded from the body portion. A total height of the body and protruding portions is substantially equal to a sum of a thickness of the conductive trace and a height of the conductive via. The height of the body portion is greater than the thickness of the conductive trace.
    Type: Grant
    Filed: April 21, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Ping Chiang, Chung-Shi Liu, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Chang-Wen Huang, Yu-Sheng Hsieh, Ching-Yu Huang
  • Publication number: 20200335439
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, a molding compound, a polymer layer, a conductive trace, a conductive via and an inductor. The semiconductor die is laterally surrounded by the molding compound. The polymer layer covers the semiconductor die and the molding compound. The conductive trace, the conductive via and the inductor are embedded in the polymer layer. The conductive via extends from a top surface of the conductive trace to a top surface of the polymer layer. The inductor has a body portion extending horizontally and a protruding portion protruded from the body portion. A total height of the body and protruding portions is substantially equal to a sum of a thickness of the conductive trace and a height of the conductive via. The height of the body portion is greater than the thickness of the conductive trace.
    Type: Application
    Filed: April 21, 2019
    Publication date: October 22, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chung-Shi Liu, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Chang-Wen Huang, Yu-Sheng Hsieh, Ching-Yu Huang
  • Publication number: 20200258799
    Abstract: A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Patent number: 10636713
    Abstract: Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Shou-Zen Chang, Albert Wan, Yu-Sheng Hsieh
  • Publication number: 20200075526
    Abstract: Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20200020628
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Yu Huang, Han-Ping Pu, Ming-Kai Liu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Patent number: 10504865
    Abstract: Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Kai Liu, Han-Ping Pu, Ting-Chu Ko, Yung-Ping Chiang, Chang-Wen Huang, Yu-Sheng Hsieh
  • Publication number: 20190279951
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.
    Type: Application
    Filed: May 30, 2019
    Publication date: September 12, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Ping CHIANG, Yi-Che CHIANG, Nien-Fang WU, Min-Chien HSIAO, Chao-Wen SHIH, Shou-Zen CHANG, Chung-Shi LIU, Chen-Hua YU
  • Patent number: 10319692
    Abstract: A method for manufacturing a semiconductor structure includes: receiving a semiconductive substrate with a post passivation interconnect including an oval landing area; forming a first conductor on the oval landing area; forming a polymer layer above the semiconductive substrate, thereby surrounding a portion of the first conductor; polishing the polymer layer and the first conductor in order to form a planarized surface; and forming a second conductor on the polished first conductor.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yung-Ping Chiang, Chao-Wen Shih, Hao-Yi Tsai, Mirng-Ji Lii
  • Patent number: 10312203
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Ping Chiang, Nien-Fang Wu, Min-Chien Hsiao, Yi-Che Chiang, Chao-Wen Shih, Shou-Zen Chang, Chung-Shi Liu, Chen-Hua Yu