Patents by Inventor Yung Ryu
Yung Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10804037Abstract: A method of manufacturing a multilayer ceramic electronic component includes: preparing a plurality of first ceramic sheets; forming internal electrode patterns on the first ceramic sheets using a conductive paste, respectively; stacking the first ceramic sheets on which the internal electrode pattern is formed to form a ceramic body including internal electrodes disposed therein to face each other; forming electrode layers by transferring a nickel-containing sheet on both end surfaces of the ceramic body in a length direction of the ceramic body so as to be connected to the internal electrodes, respectively; forming electrically insulating layers by attaching a second ceramic sheet for forming an electrically insulating layer to the electrode layers, respectively; and preparing external electrodes by forming plating layers on one surface of the ceramic body in a thickness direction of the ceramic body, to be connected to the electrode layers, respectively.Type: GrantFiled: May 24, 2019Date of Patent: October 13, 2020Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong Park, Ki Pyo Hong, Jin Yung Ryu, Jae Yeol Choi
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Patent number: 10468185Abstract: A multilayer ceramic capacitor includes a capacitor body including a plurality of first to third internal electrodes. The first internal electrodes have opposing ends exposed at third and fourth surfaces of the capacitor body. The second internal electrodes have a portion exposed at either of fifth or sixth surfaces of the capacitor body. The third internal electrodes have portions respectively exposed at the fifth and sixth surfaces. First and second external electrodes are on the third and fourth surfaces, respectively, and are connected to the first internal electrodes. Third and fourth external electrodes are on the fifth and sixth surfaces, respectively, and are connected to the second and third internal electrodes.Type: GrantFiled: December 5, 2017Date of Patent: November 5, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Beom Seock Oh, Jin Yung Ryu, Young Ghyu Ahn, Jae Yeol Choi
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Publication number: 20190279821Abstract: A multilayer ceramic electronic component includes: a ceramic body including dielectric layers and internal electrodes, stacked to be alternately exposed to one end surface and the other end surface of the ceramic body, with each of the dielectric layers interposed therebetween; and external electrodes disposed on outer surfaces of the ceramic body. The external electrodes include electrode layers connected to the internal electrodes, electrically insulating layers disposed on the electrode layers, and plating layers disposed on one surface of the ceramic body in a thickness direction of the ceramic body and connected to the electrode layers, respectively, and the electrode layers contain nickel.Type: ApplicationFiled: May 24, 2019Publication date: September 12, 2019Inventors: Yong PARK, Ki Pyo HONG, Jin Yung RYU, Jae Yeol CHOI
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Patent number: 10347427Abstract: A multilayer ceramic electronic component includes: a ceramic body including dielectric layers and internal electrodes, stacked to be alternately exposed to one end surface and the other end surface of the ceramic body, with each of the dielectric layers interposed therebetween; and external electrodes disposed on outer surfaces of the ceramic body. The external electrodes include electrode layers connected to the internal electrodes, electrically insulating layers disposed on the electrode layers, and plating layers disposed on one surface of the ceramic body in a thickness direction of the ceramic body and connected to the electrode layers, respectively, and the electrode layers contain nickel.Type: GrantFiled: April 21, 2017Date of Patent: July 9, 2019Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Yong Park, Ki Pyo Hong, Jin Yung Ryu, Jae Yeol Choi
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Publication number: 20180350521Abstract: A multilayer ceramic capacitor includes a capacitor body including a plurality of first to third internal electrodes. The first internal electrodes have opposing ends exposed at third and fourth surfaces of the capacitor body. The second internal electrodes have a portion exposed at either of fifth or sixth surfaces of the capacitor body. The third internal electrodes have portions respectively exposed at the fifth and sixth surfaces. First and second external electrodes are on the third and fourth surfaces, respectively, and are connected to the first internal electrodes. Third and fourth external electrodes are on the fifth and sixth surfaces, respectively, and are connected to the second and third internal electrodes.Type: ApplicationFiled: December 5, 2017Publication date: December 6, 2018Inventors: Beom Seock OH, Jin Yung Ryu, Young Ghyu Ahn, Jae Yeol Choi
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Publication number: 20180068795Abstract: A multilayer ceramic electronic component includes: a ceramic body including dielectric layers and internal electrodes, stacked to be alternately exposed to one end surface and the other end surface of the ceramic body, with each of the dielectric layers interposed therebetween; and external electrodes disposed on outer surfaces of the ceramic body. The external electrodes include electrode layers connected to the internal electrodes, electrically insulating layers disposed on the electrode layers, and plating layers disposed on one surface of the ceramic body in a thickness direction of the ceramic body and connected to the electrode layers, respectively, and the electrode layers contain nickel.Type: ApplicationFiled: April 21, 2017Publication date: March 8, 2018Inventors: Yong PARK, Ki Pyo HONG, Jin Yung RYU, Jae Yeol CHOI
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Publication number: 20130258546Abstract: There are provided a multilayer ceramic electronic component and a fabrication method thereof. The multilayer ceramic component includes a ceramic main body in which internal electrodes and dielectric layers are alternately laminated; external electrodes formed on outer surfaces of the ceramic main body; intermediate layers formed on the external electrodes and including one or more selected from the group consisting of nickel, copper, and a nickel-copper alloy; and plating layers formed on the intermediate layers, whereby infiltration of a plating solution can be prevented.Type: ApplicationFiled: March 14, 2013Publication date: October 3, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Chan Kong KIM, Jin Yung RYU, Jun AH, Yong Joon KO, Woo Kyung SUNG, Jong Rock LEE
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Publication number: 20070099317Abstract: A method for manufacturing a vertical light emitting diode of the invention allows an easier process of individually separating chips. A light emitting structure is formed on a growth substrate having a plurality of device areas and at least one device isolation area. The light emitting structure has an n-type clad layer, an active layer and a p-type clad layer sequentially formed therein. Corresponding p-type electrodes are formed on the light emitting structure on the device areas. A glass substrate having through holes perforated therein is provided on the p-electrodes so that the through holes are disposed corresponding to the p-electrodes. Also, the through holes are plated with a metal material to form patterns of a plating layer on the p-electrodes. Then, the growth substrate is removed to form n-electrodes on the n-type clad layer. The glass substrate is removed via etching.Type: ApplicationFiled: September 18, 2006Publication date: May 3, 2007Inventors: Yung Ryu, Hae Hwang
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Publication number: 20070090382Abstract: A light emitting diode package is provided. A package body has a mounting part surrounded by side walls and lead electrodes on a bottom surface of the mounting part. A light emitting diode chip is mounted on the bottom surface of the mounting part and electrically connected to the lead electrodes. A resin encapsulant is filled in the mounting part to encapsulate the light emitting diode chip. At least one residual resin storage is formed on a top surface of a corresponding one of the side walls to guide and accommodate a residual resin for forming the encapsulant of a preset height. Further, a storing groove is formed on the top surface of the corresponding side wall and a guiding groove is formed to guide the residual resin to the storing groove. This produces the light emitting diode package with uniform color distribution regardless of a liquid resin amount injected.Type: ApplicationFiled: October 5, 2006Publication date: April 26, 2007Inventor: Yung Ryu
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Publication number: 20070077673Abstract: There is provided a method for manufacturing a vertically structured LED capable of performing a chip separation process with ease. In the method, a light-emitting structure is formed on a growth substrate having a plurality of device regions and at least one device isolation region, wherein the light-emitting structure has an n-type clad layer, an active layer and a p-type clad layer which are disposed on the growth substrate in sequence. A p-electrode is formed on the light-emitting structure. Thereafter, a first plating layer is formed on the p-electrode such that it connects the plurality of device isolation regions. A pattern of a second plating layer is formed on the first plating layer of the device region. The growth substrate is removed, and an n-electrode is then formed on the n-type clad layer.Type: ApplicationFiled: October 3, 2006Publication date: April 5, 2007Inventors: Hae Hwang, Yung Ryu, Da Shim, Se Ahn
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Patent number: 7147835Abstract: Disclosed herein is a small particle oxide powder for dielectrics. The oxide powder has a perovskite structure, an average particle diameter [D50(?m)] of 0.3 ?m or less, a particle size distribution of the average particle diameter within 3%, a particle size distribution satisfying a condition D99/D50<2.5, a content of OH? groups of 0.2 wt % and a C/A axial ratio of 1.006 or more. A method of manufacturing the oxide powder comprises the steps of mixing TiO2 particles and a compound solved with at least one element represented by A of the perovskite structure of ABO3; drying and pulverizing the mixture of TiO2 and the compound; calcining the pulverized mixture; adding the oxide containing the elements of the site A to the coated TiO2 particles and wet-mixing, drying and pulverizing; primarily calcining and pulverizing the pulverized powder under vacuum; and secondarily calcining and pulverizing the powder.Type: GrantFiled: July 12, 2004Date of Patent: December 12, 2006Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Dong Hwan Seo, Kang Heon Hur, Sung Hyung Kang, Jin Yung Ryu
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Publication number: 20060234411Abstract: The invention relates to a method of manufacturing a semiconductor light emitting diode. In the method, an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer are formed sequentially on a substrate. Then, a nickel oxide (NiOx) film is directly deposited on the p-type semiconductor layer via reactive sputtering or reactive deposition in an oxidizing atmosphere. Also, a light transmissible conductive oxide layer is formed on the nickel oxide film.Type: ApplicationFiled: April 7, 2006Publication date: October 19, 2006Inventors: Yung Ryu, Pil Kang
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Publication number: 20060208264Abstract: A nitride semiconductor LED improved in lighting efficiency and a fabrication method thereof, in which an n-doped semiconductor layer is formed on a substrate. An active layer is formed on the n-doped semiconductor layer to expose at least a partial area of the n-doped semiconductor layer. A p-doped semiconductor layer is formed on the active layer. A p+-doped semiconductor layer is formed on the p-doped semiconductor layer. An n+-doped semiconductor layer is formed in at least a partial upper region of the p+-doped semiconductor layer via n-dopant ion implantation. The n+-doped semiconductor layer cooperates with an underlying partial region of the p+-doped semiconductor layer to realize a reverse bias tunneling junction. Also, an upper n-doped semiconductor layer is formed on the n+-doped semiconductor layer to realize lateral current spreading. The invention can improve lighting efficiency by using the reverse bias tunneling junction and/or the lateral current spreading.Type: ApplicationFiled: May 24, 2006Publication date: September 21, 2006Inventors: Yung Ryu, Kee Yang, Bang Oh, Jin Park, Young Kim
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Publication number: 20050208686Abstract: A nitride semiconductor LED improved in lighting efficiency and a fabrication method thereof, in which an n-doped semiconductor layer is formed on a substrate. An active layer is formed on the n-doped semiconductor layer to expose at least a partial area of the n-doped semiconductor layer. A p-doped semiconductor layer is formed on the active layer. A p+-doped semiconductor layer is formed on the p-doped semiconductor layer. An n+-doped semiconductor layer is formed in at least a partial upper region of the p+-doped semiconductor layer via n-dopant ion implantation. The n+-doped semiconductor layer cooperates with an underlying partial region of the p+-doped semiconductor layer to realize a reverse bias tunneling junction. Also, an upper n-doped semiconductor layer is formed on the n+-doped semiconductor layer to realize lateral current spreading. The invention can improve lighting efficiency by using the reverse bias tunneling junction and/or the lateral current spreading.Type: ApplicationFiled: June 25, 2004Publication date: September 22, 2005Inventors: Yung Ryu, Kee Yang, Bang Oh, Jin Park, Young Kim
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Publication number: 20050179045Abstract: Disclosed is a nitride semiconductor LED and a fabrication method thereof. An n-doped semiconductor layer, an active layer, a p-doped semiconductor layer and a p+-doped semiconductor layer are formed in their order on a substrate. A resultant semiconductor structure is mesa-etched to expose a partial area of the n-doped semiconductor layer. The p+-doped semiconductor layer and the exposed area of the n-doped semiconductor layer are n-doped at a high concentration to form first and second n+-doped regions, respectively. P- and n-electrodes are formed on the first and second n+-doped regions, respectively. Then, reverse bias is created to improve an ohmic contact structure between a semiconductor layer and a metal electrode thereby lowering drive voltage while raising overvoltage resistance and luminance.Type: ApplicationFiled: June 2, 2004Publication date: August 18, 2005Inventors: Yung Ryu, Kee Yang, Bang Oh, Jin Park