Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.

Abstract: A communication system and an operation method thereof are provided. The transmitting device transmits the current data unit and the transmitted data verification information to the receiving device through the communication interface, and records the current data unit in an FIFO buffer. The receiving device counts the received data identification value by itself based on the current data unit received from the communication interface. The receiving device uses the received data identification value and the transmitted data verification information to check whether the current data unit received from the communication interface has errors. When the current data unit is in error, the receiving device returns an error flag to the transmitting device so that the transmitting device suspends the transmission of the new data unit, and transmits the buffered data unit recorded in the FIFO buffer to the receiving device through the communication interface.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: A communication system and an operation method thereof are provided. The transmitting device transmits the current data unit and the transmitted data verification information to the receiving device through the communication interface, and records the current data unit in an FIFO buffer. The receiving device counts the received data identification value by itself based on the current data unit received from the communication interface. The receiving device uses the received data identification value and the transmitted data verification information to check whether the current data unit received from the communication interface has errors. When the current data unit is in error, the receiving device returns an error flag to the transmitting device so that the transmitting device suspends the transmission of the new data unit, and transmits the buffered data unit recorded in the FIFO buffer to the receiving device through the communication interface.

Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

Abstract: An electronic system, an integrated circuit die and an operation method thereof are provided. The integrated circuit die includes a plurality of interface circuit slices and a merging circuit. The transmission data stream sent from the transmitter die is split into a plurality of sub-data streams. Each of the interface circuit slices provides a physical layer to receive the corresponding one of the sub-data streams. The merging circuit is coupled to the interface circuit slices to receive the sub-data streams. The merging circuit merges the sub-data streams from the interface circuit slices back to the original data corresponding to the transmission data stream to be provided to an application layer. The merging circuit aligns the sub-data streams from the interface circuit slices in timing to mitigate different delays of the interface circuit slices.

Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.

Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.

Abstract: A frame decoding circuit implemented in an IC die includes a frame synchronizer, receiving an input clock signal and an input frame signal in serial form, to provide an output clock signal. A phase shift of the output clock signal is adjusted according to a detected code by sampling the input frame signal at a center point for every two bits and the detected code being not a correct type. The input clock signal is divided in frequency with the phase shift for providing the output clock signal. A de-serializer unit receives the input frame signal, the input data, the output clock signal from the frame synchronizer, a delay-locked-loop clock signal to de-serialize the input frame signal and the input data for output.

Abstract: An interface device and an interface method for interfacing between a master device and a slave device is provided. The master device generates command and the slave device generates data according to the command. The interface device includes a master interface and a slave interface. The master interface is coupled to the master device and configured to send the command to the slave device and/or receive the data from the slave device. The slave interface is coupled to the slave device and configured to receive the command from the master device and/or send the data to the master device. The master interface and the slave interface are driven by a clock generated by a clock generator. The master interface and the slave interface are electrically connected by one or plurality of bonds and/or TSVs.

Abstract: A method for determining performance of an integrated circuit (IC) is disclosed herein. The method includes following operations: disposing hardware performance monitors (HPMs) in each of ICs, in which each of HPMs generates a value for generating the performance of the IC; providing a performance function including of terms according to values generated by the HPMs, in which a weight is associated with each of terms; determining the weight of each of terms according to a first set of ICs of the ICs, wherein the performance of each of the ICs is known; and determining the performance of a first ICs of the ICs according to the performance function, wherein the performance function and the weights are built into the first ICs.

Abstract: The present invention discloses a method of to generate transaction ID(s) in a bus interconnection design. An encoding table for each slave can be derived by calculating all possible transactions from all the masters to the slave so as to determine the minimum width of the transaction ID received by the slave in the interconnecting bus design, thereby avoiding the routing congestion in the interconnecting bus.

Abstract: A method of determining the performance of a chip of an integrated-circuit design comprises instantiating a plurality of HPM in the integrated-circuit design to generate the performance of the chip according to a performance function defined by a polynomial comprising a plurality of terms, wherein each term of the polynomial comprises an exponent of a value generated by a corresponding one of the plurality of HPM(s) and a corresponding coefficient, wherein the coefficients are determined through a regression process with sample chips of the integrated-circuit design having known performance, so that the performance of each chip other than the sample chips can be determined by the performance function and the values of the plurality of HPM(s) of the chip.

Abstract: A method for determining performance of an integrated circuit (IC) is disclosed herein. The method includes following operations: disposing hardware performance monitors (HPMs) in each of ICs, in which each of HPMs generates a value for generating the performance of the IC; providing a performance function including of terms according to values generated by the HPMs, in which a weight is associated with each of terms; determining the weight of each of terms according to a first set of ICs of the ICs, wherein the performance of each of the ICs is known; and determining the performance of a first ICs of the ICs according to the performance function, wherein the performance function and the weights are built into the first ICs.