Abstract: A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.

Abstract: The disclosure provides a communication system between dies and a repairing method for lanes between dies. The communication system includes a transmitting device disposed on a first die and a receiving device disposed on a second die. During the transmission process in which the transmitting device transmits a data unit stream to the receiving device through a native lane, after the native lane is determined to be a degraded lane, the transmitting device transmits a synchronization flag to the receiving device through a redundant lane to notify a repair time point. During the uninterrupted transmission process of the data unit stream, the transmitting device uses the redundant lane instead of the degraded lane based on the repair time point, and the receiving device uses the redundant lane instead of the degraded lane based on the repair time point notified by the synchronization flag.

Abstract: A die-to-die communication system and an operation method thereof are provided. The die-to-die communication system includes a transmitting device disposed at a first die and a receiving device disposed at a second die, wherein the first die and second die are disposed in a same integrated circuit package. The receiving device is coupled to the transmitting device via a communication interface. The transmitting device transmits a data unit stream to a data channel in the communication interface. The receiving device receives the data unit stream from the data channel in the communication interface. The receiving device returns transmission management information to the transmitting device via a feedback channel different from the data channel in the communication interface. In various embodiments, the transmission management information includes flow control information and/or error replay information.

Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.

Abstract: The disclosure provides a data bus inversion (DBI) encoding device and a DBI encoding method. The DBI encoding device includes a comparator circuit, a first controllable inverting circuit and a second controllable inverting circuit. The comparator circuit checks the number of the different bits between a first raw data and a second raw data. Based on the number of the different bits, the first controllable inversion circuit determines whether to invert a first DBI bit corresponding to the first raw data as a second DBI bit corresponding to the second raw data. The second controllable inversion circuit determines, based on the second DBI bit, whether to adopt the second raw data as a second encoded data corresponding to the second raw data, or invert the second raw data to generate the second encoded data.

Abstract: A communication system and an operation method thereof are provided. A transmitting device transmits a data unit to a receiving device through a data channel of a communication interface. The transmitting device calculates an original verification information unit of the data unit and synchronously transmits the original verification information unit to the receiving device through a verification information channel of the communication interface based on a transmission timing of the data unit in the data channel. After receiving a current data unit and before receiving a next data unit, the receiving device verifies whether the current data unit received from the data channel has errors in real time based on a current original verification information unit corresponding to the current data unit.

Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.

Abstract: A communication system and an operation method thereof are provided. The transmitting device transmits the current data unit and the transmitted data verification information to the receiving device through the communication interface, and records the current data unit in an FIFO buffer. The receiving device counts the received data identification value by itself based on the current data unit received from the communication interface. The receiving device uses the received data identification value and the transmitted data verification information to check whether the current data unit received from the communication interface has errors. When the current data unit is in error, the receiving device returns an error flag to the transmitting device so that the transmitting device suspends the transmission of the new data unit, and transmits the buffered data unit recorded in the FIFO buffer to the receiving device through the communication interface.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: A communication system and an operation method thereof are provided. The transmitting device transmits the current data unit and the transmitted data verification information to the receiving device through the communication interface, and records the current data unit in an FIFO buffer. The receiving device counts the received data identification value by itself based on the current data unit received from the communication interface. The receiving device uses the received data identification value and the transmitted data verification information to check whether the current data unit received from the communication interface has errors. When the current data unit is in error, the receiving device returns an error flag to the transmitting device so that the transmitting device suspends the transmission of the new data unit, and transmits the buffered data unit recorded in the FIFO buffer to the receiving device through the communication interface.

Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

Abstract: An electronic system, an integrated circuit die and an operation method thereof are provided. The integrated circuit die includes a plurality of interface circuit slices and a merging circuit. The transmission data stream sent from the transmitter die is split into a plurality of sub-data streams. Each of the interface circuit slices provides a physical layer to receive the corresponding one of the sub-data streams. The merging circuit is coupled to the interface circuit slices to receive the sub-data streams. The merging circuit merges the sub-data streams from the interface circuit slices back to the original data corresponding to the transmission data stream to be provided to an application layer. The merging circuit aligns the sub-data streams from the interface circuit slices in timing to mitigate different delays of the interface circuit slices.

Abstract: A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.

Abstract: A physical analysis method, a sample for physical analysis and a preparing method thereof are provided. The preparing method of the sample for physical analysis includes: providing a sample to be inspected; and forming a contrast enhancement layer on a surface of the sample to be inspected. The contrast enhancement layer includes a plurality of first material layers and a plurality of second material layers stacked upon one another. The first material layer and the second material layer are made of different materials. Each one of the first and second material layers has a thickness that does not exceed 0.1 nm. In an image captured by an electron microscope, a difference between an average grayscale value of a surface layer image of the sample to be inspected and an average grayscale value of an image of the contrast enhancement layer is at least 50.

Abstract: An interface for a semiconductor device is provided. The semiconductor device has a master device and multiple slave devices as stacked up with electric connection. The interface includes a master interface, implemented in the master device and including a master interface circuit with a master bond pattern. Further, a slave interface is implemented in each slave device and includes a slave interface circuit with a slave bond pattern to correspondingly connect to the master bond pattern. A clock route is to transmit a clock signal through the master interface and the slave interface. The master device transmits a command and a selecting slave identification through the master interface to all the slave interfaces. One of the slave devices corresponding to the selecting slave identification executes the command and responds a result back to the master device through the slave interfaces and the master interface.

Abstract: A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.

Abstract: A semiconductor device with an interface includes a master device and a plurality of slave devices. The master device includes a master interface. The slave devices are stacked on the master device one after one as a three-dimension (3D) stack. Each of the slave devices includes a slave interface and a managing circuit, the master interface and the slave interfaces form the interface for passing signals in communication between the master device and the slave devices. The managing circuit of a current one of the slave devices drives a next one of the slave devices. An operation command received at the current one of the slave devices is just passed to the next one of the slave devices through the interface. A response from the current one of the slave devices is passed back to the master device through the interface.

Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.