Patents by Inventor Yung Sheng Zou

Yung Sheng Zou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071963
    Abstract: A semiconductor device assembly is provided. The assembly includes a package substrate which has a tunneled interconnect structure. The tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. The assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. The joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Yun Ting Hsu, Chong Leong Gan, Min Hua Chung, Yung Sheng Zou
  • Publication number: 20230207490
    Abstract: A semiconductor device assembly including a substrate, a surface-mount device (SMD) electrical component attached to the substrate is provided. The SMD electrical component includes a first contact and a second contact, and at least a first wire bond electrically and physically coupled directly to the first contact.
    Type: Application
    Filed: October 28, 2022
    Publication date: June 29, 2023
    Inventors: Yung Sheng Zou, Yun Ting Hsu
  • Publication number: 20230062160
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor devices include a package substrate, a stack of dies carried by the package substrate, and one or more radiation shields configured to absorb neutrons from neutron radiation incident on the semiconductor device. The radiation shields can include one or more walls attached to a perimeter portion of the package substrate at least partially surrounding the stack of dies and/or a lid carried over the stack of dies. Each of the radiation shields can include hydrocarbon materials, boron, lithium, gadolinium, cadmium, and like materials that effectively absorb neutrons from neutron radiation. In some embodiments, the semiconductor devices also include a molding material over the stack of dies and the radiation shields, and a hydrocarbon coating over an external surface of the mold material.
    Type: Application
    Filed: April 11, 2022
    Publication date: March 2, 2023
    Inventors: Chong Leong Gan, Min Hua Chung, Yung Sheng Zou, Lu Fu Lin, Li Jao
  • Patent number: 11515222
    Abstract: Semiconductor devices having flow controllers configured to reduce mitigation of mold material between stacked layers, and associated systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a package substrate that has first and second surfaces. First and second die stacks are formed on the first surface and are adjacent to each other. A portion of the first surface extends between the first and second die stacks. A layer of material is adhered to top surfaces of the first and second die stacks and extends at a distance above the package substrate to form a tunnel between the layer of material, opposing sidewalls of the die stacks, and the package substrate. The semiconductor device further includes a flow controller that is adhered to at least a portion of the first surface inside the tunnel that reduces a cross-sectional surface area of at least a portion of the tunnel.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Lu Fu Lin, Yung Sheng Zou, Chong Leong Gan, Li Jao, Min Hua Chung
  • Publication number: 20220208625
    Abstract: Semiconductor devices having flow controllers configured to reduce mitigation of mold material between stacked layers, and associated systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a package substrate that has first and second surfaces. First and second die stacks are formed on the first surface and are adjacent to each other. A portion of the first surface extends between the first and second die stacks. A layer of material is adhered to top surfaces of the first and second die stacks and extends at a distance above the package substrate to form a tunnel between the layer of material, opposing sidewalls of the die stacks, and the package substrate. The semiconductor device further includes a flow controller that is adhered to at least a portion of the first surface inside the tunnel that reduces a cross-sectional surface area of at least a portion of the tunnel.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Lu Fu Lin, Yung Sheng Zou, Chong Leong Gan, Li Jao, Min Hua Chung