Patents by Inventor Yung-Shun Liao

Yung-Shun Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940737
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Patent number: 9117714
    Abstract: An exemplary wafer level package comprises a semiconductor wafer with a plurality of semiconductor chips of perfect polygonal shapes thereon. A circuit-free area is defined over the semiconductor wafer to electrically isolate the semiconductor chips. A dam structure is substantially formed over the circuit-free area, wherein a portion of the dam structure formed around an edge of the semiconductor wafer is formed with a plurality via holes therein. A transparent substrate is formed over the semiconductor wafer, defining a plurality of cavities between the semiconductor chips and the transparent substrate, wherein the transparent substrate is supported by the dam structure.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: August 25, 2015
    Assignee: VisEra TECHNOLOGIES COMPANY LIMITED
    Inventors: Fu-Tien Weng, Yung-Shun Liao, Yi-Chuan Lo, Bii-Cheng Chang
  • Publication number: 20090102005
    Abstract: An exemplary wafer level package comprises a semiconductor wafer with a plurality of semiconductor chips of perfect polygonal shapes thereon. A circuit-free area is defined over the semiconductor wafer to electrically isolate the semiconductor chips. A dam structure is substantially formed over the circuit-free area, wherein a portion of the dam structure formed around an edge of the semiconductor wafer is formed with a plurality via holes therein. A transparent substrate is formed over the semiconductor wafer, defining a plurality of cavities between the semiconductor chips and the transparent substrate, wherein the transparent substrate is supported by the dam structure.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 23, 2009
    Inventors: Fu-Tien Weng, Yung-Shun Liao, Yi-Chuan Lo, Bii-Cheng Chang
  • Patent number: 7422970
    Abstract: A method is provided for modifying a circuit containing a plurality of electrodes, within a substrate, comprising the steps of: (a) selecting at least two electrodes for making a connection; (b) removing materials covering the electrodes with a focused ion beam (FIB) or a laser to form contact holes for respectively exposing the electrodes; (c) depositing in the contact holes a conductive material for forming electrically conductive piers, by applying the focused ion beam (FIB) or laser, with gas molecules ejected from a nozzle; (d) disposing an electrically conductive viscid material over each of the electrically conductive piers; and (e) disposing an electrically conductive bridge floor to connect with the electrically conductive viscid material to form an electrically conductive bridge.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: September 9, 2008
    Assignee: Integrated Service Technology Inc.
    Inventors: Wei-Been Yu, Yung-Shun Liao, Hsin-Sheng Liao
  • Publication number: 20070164236
    Abstract: The present invention relates to a method for retrieving a signal from a circuit within a substrate. The method comprising steps of: (a) selecting at least one from the plurality of electrodes for signal retrieving; (b) removing materials covering said selected electrode with a focused ion beam (FIB) or a laser to form contact hole for exposing said selected electrode; (c) depositing in said contact hole a conductive material for forming electrically conductive pier by applying said focused ion beam (FIB) or a laser over gas molecules; (d) disposing an electrically conductive viscid material over each electrically conductive pier; and (e) connecting the electrically conductive viscid material with a conductive wire. Thus, the signal could be retrieved from the electrically conductive wire.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 19, 2007
    Inventors: Wei-Been Yu, Yung-Shun Liao, Hsin-Sheng Liao
  • Publication number: 20070166842
    Abstract: The present invention relates to a method for modifying a circuit within a substrate, and the circuit includes a plurality of electrodes. The method includes: (a) selecting at least two from the plurality of electrodes for making connection; (b) removing materials covering said selected electrodes with a focused ion beam (FIB) or a laser to form contact holes for respectively exposing said selected electrodes; (c) depositing in said contact holes a conductive material for forming electrically conductive piers by applying said focused ion beam (FIB) or a laser with gas molecules ejected from a nozzle; (d) disposing an electrically conductive viscid material over each of said electrically conductive piers; and (e) disposing an electrically conductive bridge floor to connect with each of the electrically conductive viscid material to form an electrically conductive bridge.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 19, 2007
    Inventors: Wei-Been Yu, Yung-Shun Liao, Hsin-Sheng Liao