Patents by Inventor Yung-Tai TSAI

Yung-Tai TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979130
    Abstract: A transmitter circuit is provided. The transmitter circuit has a first transmission node and a second transmission node and includes a first resistor, a second resistor, a third resistor, a fourth resistor, and a driving circuit. The driving circuit includes a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group. The first resistor is coupled between a first output terminal and the first transmission node. The second resistor is coupled between a second output terminal and the second transmission node. The third resistor is coupled between a third output terminal and the first transmission node. The fourth resistor is coupled between a fourth output terminal and the second transmission node. The first, second, third, and fourth transistor groups are coupled to a first and a second reference voltages and electrically connected to the first, second, third, and fourth output terminals, respectively.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: May 7, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hung-Chen Chu, Chien-Hui Tsai, Yung-Tai Chen
  • Patent number: 11929747
    Abstract: A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a clamping circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and a pair of output terminals for outputting a pair of output signals. The clamping circuit is coupled between a medium-voltage terminal and the pair of output terminals and limits the minimum voltage of the pair of output signals to the medium voltage. The protection circuit is set between the latch circuit and the input circuit, and prevents an excessive voltage drop between the input circuit and the pair of output terminals. The input circuit includes an input transistor pair coupled between the protection circuit and a low-voltage terminal having a low voltage. The input transistor pair receives a pair of input signals and operates accordingly.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 12, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-Hui Tsai, Hung-Chen Chu, Yung-Tai Chen
  • Patent number: 9419050
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A second surface of the wafer is adhered to an ultraviolet tape on a frame, and the temporary bonding layer and the carrier are removed. A protection tape is adhered to the first surface of the wafer. An ultraviolet light is used to irradiate the ultraviolet tape. A dicing tape is adhered to the protection tape and the frame, and the ultraviolet tape is removed. A first cutter is used to dice the wafer from the second surface of the wafer, such that plural chips and plural gaps between the chips are formed. A second cutter with a width smaller than the width of the first cutter is used to cut the protection tape along the gaps.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: August 16, 2016
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Shu-Ming Chang, Yung-Tai Tsai, Tsang-Yu Liu
  • Patent number: 9275963
    Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 1, 2016
    Assignee: XINTEC INC.
    Inventors: Yung-Tai Tsai, Shu-Ming Chang, Chun-Wei Chang, Chien-Hui Chen, Tsang-Yu Liu, Yen-Shih Ho
  • Publication number: 20150340403
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A second surface of the wafer is adhered to an ultraviolet tape on a frame, and the temporary bonding layer and the carrier are removed. A protection tape is adhered to the first surface of the wafer. An ultraviolet light is used to irradiate the ultraviolet tape. A dicing tape is adhered to the protection tape and the frame, and the ultraviolet tape is removed. A first cutter is used to dice the wafer from the second surface of the wafer, such that plural chips and plural gaps between the chips are formed. A second cutter with a width smaller than the width of the first cutter is used to cut the protection tape along the gaps.
    Type: Application
    Filed: May 4, 2015
    Publication date: November 26, 2015
    Inventors: Yen-Shih HO, Shu-Ming CHANG, Yung-Tai TSAI, Tsang-Yu LIU
  • Publication number: 20140252659
    Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 11, 2014
    Applicant: XINTEC INC.
    Inventors: Yung-Tai TSAI, Shu-Ming CHANG, Chun-Wei CHANG, Chien-Hui CHEN, Tsang-Yu LIU, Yen-Shih HO