Abstract: A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.

Abstract: A non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.

Abstract: A MRAM cell structure includes a bottom electrode; a magnetic tunnel junction unit disposed on the bottom electrode; a top electrode disposed on the magnetic tunnel junction unit; and a blocking layer disposed on the top electrode, wherein the blocking layer is wider than the magnetic tunnel junction unit for preventing against formation of a short circuit between a contact and the magnetic tunnel junction unit.

Abstract: A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a floating gate over a semiconductor substrate, a first capacitor comprising a first plate, the floating gate, and a dielectric therebetween, a second capacitor comprising a second plate, the floating gate, and a dielectric therebetween, a third capacitor comprising a third plate connected to the floating gate, and a fourth plate, wherein the third and fourth plates are formed in metallization layers over the semiconductor substrate. The first plate of the first capacitor includes a first doped region and a second doped region in the semiconductor substrate. The non-volatile memory cell further includes a transistor comprising a gate electrode over the semiconductor substrate, wherein a source/drain region of the transistor is connected to the first doped region of the first capacitor.

Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A tunneling oxide layer is formed overlying a semiconductor substrate. A first polysilicon layer, an interpoly oxide layer and then a second polysilicon layer are deposited. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions that are deeper and less abrupt than the drain junctions.

Abstract: A method of fabricating an LCD-on-silicon pixel device, comprising the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.

Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A tunneling oxide layer is formed overlying a semiconductor substrate. A first polysilicon layer, an interpoly oxide layer and then a second polysilicon layer are deposited. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions that are deeper and less abrupt than the drain junctions.

Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.

Abstract: A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjacent to NMOS devices and angle implantation of n-type impurities into corners of STI regions that are adjacent to PMOS devices.

Abstract: A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. A layer of pad oxide is created over the surface of a silicon substrate, a layer of silicon nitride is deposited and patterned such that the layer of pad oxide is exposed where Shallow Trench Isolation regions are to be created. A layer of photoresist is deposited, patterned and etched to expose the surface of the p-well that has been created in the surface of the substrate, p-type impurity is then implanted into the corners of the STI region that are adjacent to NMOS device that is to be created over the p-well. The process is then repeated in reverse image order to perform a n-type implant into the corners of the STI region that are adjacent to the PMOS device that is to be created over a n-well region that has been created in the surface of the substrate.

Abstract: A method of fabricating an LCD-on-silicon pixel device, comprising the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.

Abstract: a new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.

Abstract: a new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.

Abstract: a new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.

Abstract: A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions.

Abstract: A trench transistor formation method for creating source and drain regions and source and drain extension regions having an idealized doping profile using a single dopant implantation step. In one embodiment, the present invention is comprised of a method which includes forming a trench having sidewalls and a bottom into a substrate. The present embodiment also recites forming sidewalls spacer regions along at least a portion of the sidewalls of the trench. Subsequently, the present embodiment forms a gate dielectric along at least a portion of the bottom of the trench, and deposits a gate metal within the trench. The present embodiment then subjects the substrate to an etching process such that the top surface of the substrate is lower than the top surface of the sidewall spacer regions formed along the sidewalls of the trench.

Abstract: A method of fabricating an LCD-on-silicon pixel device including the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.

Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.

Abstract: A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions.

Abstract: A method is provided for manufacturing a multiple voltage flash memory integrated circuit structure on a semiconductor substrate having a plurality of shallow trench isolations and a floating gate structure. A first dielectric layer is formed and a portion removed to expose regions of the semiconductor substrate for first and second low voltage devices. A second dielectric layer is formed over the first dielectric layer and the semiconductor substrate and a portion removed to expose a region of the semiconductor substrate for the second low voltage device. A third dielectric layer is formed over the second dielectric layer to form: a floating gatedevice including the first, second, and third dielectric layers; a first voltage device including the first, second, and third dielectric layers; a second voltage device including the second and third dielectric layers; and a third voltage device including the third dielectric layer.