Patents by Inventor Yung Tsai

Yung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200246291
    Abstract: The inventors have unexpectedly discovered that shock and/or potential multi-organ failure due to shock can be effectively treated by administration of liquid high-dose protease inhibitor formulations to a location upstream of where pancreatic proteases are introduced into the gastrointestinal tract. Most preferably, administration is directly to the stomach, for example, via nasogastric tube under a protocol effective to treat shock by such administration without the need of providing significant quantities of the protease inhibitor to the jejunum and/or ileum.
    Type: Application
    Filed: November 21, 2018
    Publication date: August 6, 2020
    Applicants: InflammaGen, LLC, The Regents of the University of California
    Inventors: Geert W. Schmid-Schonbein, Yung-Tsai (Andrew) Lee, Jeng Wei
  • Publication number: 20200249101
    Abstract: A thermal sensor package for earbuds includes two thermopile sensor elements on a single thermopile sensor chip, and the two thermopile sensor elements are separated by a block wall of a cap. One of the thermopile sensor elements senses external infrared thermal radiation through a window of the cap, and the other thermopile sensor element senses internal infrared thermal radiation from a package structure as a basis for correcting compensation. Therefore, the foregoing thermal sensor package for earbuds can quickly correct a measurement error caused by the package structure to improve the measurement accuracy. In addition, the forgoing thermal sensor package for earbuds has a simple packaging step and is easy to arrange a silicon based infrared lens to expand its application.
    Type: Application
    Filed: June 14, 2019
    Publication date: August 6, 2020
    Inventors: Chein-Hsun WANG, Ming LE, Yu-Chih LIANG, Tung Yang LEE, Chih-Yung TSAI
  • Patent number: 10535664
    Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: January 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Wei-Hsin Liu, Chia-Lung Chang, Yi-Wei Chen, Han-Yung Tsai
  • Publication number: 20190363093
    Abstract: A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
    Type: Application
    Filed: June 19, 2018
    Publication date: November 28, 2019
    Inventors: Po-Chun Chen, Wei-Hsin Liu, Chia-Lung Chang, Yi-Wei Chen, Han-Yung Tsai
  • Publication number: 20190280095
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
    Type: Application
    Filed: April 3, 2018
    Publication date: September 12, 2019
    Inventors: Po-Chun Chen, Chia-Lung Chang, Yi-Wei Chen, Wei-Hsin Liu, Han-Yung Tsai
  • Patent number: 10332888
    Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 25, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Han-Yung Tsai, Tzu-Chin Wu
  • Publication number: 20190175532
    Abstract: The inventors have unexpectedly discovered that shock and/or potential multi-organ failure due to shock can be effectively treated by administration of liquid high-dose protease inhibitor formulations to a location upstream of where pancreatic proteases are introduced into the gastrointestinal tract. Most preferably, administration is directly to the stomach, for example, via nasogastric tube under a protocol effective to treat shock by such administration without the need of providing significant quantities of the protease inhibitor to the jejunum and/or ileum.
    Type: Application
    Filed: November 21, 2018
    Publication date: June 13, 2019
    Applicants: InflammaGen, LLC, The Regents of the University of California
    Inventors: Geert W. Schmid-Schonbein, Yung-Tsai (Andrew) Lee, Jeng Wei
  • Publication number: 20190148382
    Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Han-Yung Tsai, Tzu-Chin Wu
  • Patent number: 10249706
    Abstract: The present invention provides a semiconductor structure comprising a substrate, a cell region defined on the substrate, a plurality of lower electrodes of the capacitor structures located in the cell region, an top support structure, contacting a top region of the lower electrode structure, and at least one middle support structure located between the substrate and the top support structure, contacting a middle region of the lower electrode structure, wherein when viewed in a top view, the top support structure and the middle support structure do not completely overlapped with each other.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 2, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Lung Chang, Wei-Hsin Liu, Po-Chun Chen, Yi-Wei Chen, Han-Yung Tsai, Tzu-Chin Wu, Shih-Fang Tzou
  • Patent number: 10137100
    Abstract: The inventors have unexpectedly discovered that shock and/or potential multi-organ failure due to shock can be effectively treated by administration of liquid high-dose protease inhibitor formulations to a location upstream of where pancreatic proteases are introduced into the gastrointestinal tract. Most preferably, administration is directly to the stomach, for example, via nasogastric tube under a protocol effective to treat shock by such administration without the need of providing significant quantities of the protease inhibitor to the jejunum and/or ileum.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: November 27, 2018
    Assignees: The Regents of the University of California, Inflammagen, LLC
    Inventors: Geert W. Schmid-Schonbein, Yung-Tsai (Andrew) Lee, Jeng Wei
  • Patent number: 9955578
    Abstract: A circuit structure includes a patterned circuit layer, a patterned insulating layer and a support plate. The patterned insulating layer covers a portion of the patterned circuit layer, wherein an upper surface of the patterned circuit layer is aligned with a top surface of the patterned insulating layer. The support plate is disposed on a bottom surface of the patterned insulating layer, wherein the support plate, the patterned insulating layer and the patterned circuit layer define a plurality of air gaps.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: April 24, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Chia-Chan Chang, Gwo-Chaur Chen, Yung-Tsai Chen
  • Publication number: 20180065828
    Abstract: A wire-shaped body winding mechanism provided by the present invention includes multiple rotary shafts for winding a wire-shaped body, where a main shaft member serves as a revolution central shaft and two split shaft members serve as rotation central shafts. The wire-shaped body is wound on the split shaft members and thus can be coiled or released with rotation of the main shaft member. Relative movement between the split shaft members and the wire-shaped body is realized through rotation of the split shaft members, and thus the wire-shaped body can move smoothly.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 8, 2018
    Inventors: Yung-Tsai CHUO, Chi-Pin CHOU
  • Publication number: 20180065829
    Abstract: The present invention provides a motion platform having a wire-shaped body winding mechanism, where the wire-shaped body winding mechanism is combined on one side of the motion platform to wind related pipelines, which prevents problems in operating security caused by dropping of overlong pipelines, makes the peripheral environment of the motion platform neat, and causes no vibration or noise pollution.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 8, 2018
    Inventors: Yung-Tsai CHUO, Chi-Pin CHOU
  • Publication number: 20180032299
    Abstract: The present invention provides a pairing system and a pairing method for a plurality of display devices and a plurality of multi-media devices that can make the pairing process between the plurality of display devices and the plurality of multi-media devices more convenient and easier for users. The pairing system comprises: a plurality of multi-media devices and a control device. The plurality of multi-media devices are respectively coupled to the plurality of display devices, and utilized for transmitting signals to the plurality of display devices, respectively. The control device is utilized for automatically pairing the plurality of display devices with the plurality of multi-media devices. The pairing method comprises: utilizing a control device to automatically pair the plurality of display devices with the plurality of multi-media devices by controlling the plurality of multi-media devices to transmit a plurality of identifying signals to the plurality of display devices.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Inventors: Chi-Fu Liu, Yung-Tsai Wang, Chia-Chin Wang
  • Patent number: 9850996
    Abstract: A motor-incorporating reducer includes a main body, a rotational actuating member, a flex spline, and an circular spline. The rotational actuating member has a rotating shaft, a wave generator, and a motor. The rotating shaft passes through the main body, and the elliptic wheel is integratedly formed around the rotating shaft. The motor has a magnetic motor rotator that is integratedly formed on the rotating shaft. With the integrated structure, the rotating shaft, the elliptic wheel, and the motor rotator can stably perform rotation, thereby eliminating the risk that the three, when formed separated and assembled, would become non-coaxial due to the resultant tolerance after assembly and have eccentric rotation, and in turn preventing adverse effects on the drive's output torque due to non-coaxial rotation and extending the drive's service life.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: December 26, 2017
    Assignee: Hiwin Technologies Corp.
    Inventors: Yung-Tsai Chuo, Po-Jung Huang
  • Patent number: 9774237
    Abstract: A slide-block-type shaft linear motor platform includes a mover and a stator. An air gap is defined between the mover and the stator. The air gap can communicate with outer side via a fluid inlet space. Accordingly, air convection can take place between the heat source, that is, the winding inside the mover and the outer side. Therefore, the heat generated by the winding can be continuously dissipated to prevent the components from deforming due to the heat. In this case, the precision of operation can be ensured and the performance of the motor will not deteriorate due to the heat.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: September 26, 2017
    Assignee: HIWIN MIKROSYSTEM CORP.
    Inventors: Yung-Tsai Chuo, Yu-Jung Chang, Sheng-Shiun Huang
  • Publication number: 20170251551
    Abstract: A circuit structure includes a patterned circuit layer, a patterned insulating layer and a support plate. The patterned insulating layer covers a portion of the patterned circuit layer, wherein an upper surface of the patterned circuit layer is aligned with a top surface of the patterned insulating layer. The support plate is disposed on a bottom surface of the patterned insulating layer, wherein the support plate, the patterned insulating layer and the patterned circuit layer define a plurality of air gaps.
    Type: Application
    Filed: May 12, 2017
    Publication date: August 31, 2017
    Applicant: Unimicron Technology Corp.
    Inventors: Chia-Chan Chang, Gwo-Chaur Chen, Yung-Tsai Chen
  • Publication number: 20170231935
    Abstract: The inventors have unexpectedly discovered that shock and/or potential multi-organ failure due to shock can be effectively treated by administration of liquid high-dose protease inhibitor formulations to a location upstream of where pancreatic proteases are introduced into the gastrointestinal tract. Most preferably, administration is directly to the stomach, for example, via nasogastric tube under a protocol effective to treat shock by such administration without the need of providing significant quantities of the protease inhibitor to the jejunum and/or ileum.
    Type: Application
    Filed: October 26, 2016
    Publication date: August 17, 2017
    Applicants: InflammaGen, LLC, The Regents of the University of California
    Inventors: Geert W. Schmid-Schonbein, Yung-Tsai (Andrew) Lee, Jeng Wei
  • Patent number: 9691699
    Abstract: A method for manufacturing a circuit structure is described as follows. Two patterned circuit layers are formed on a core layer. The patterned circuit layers are located on two opposite surfaces of the core layer. A patterned insulating layer is respectively formed on each of the patterned circuit layers. The patterned insulating layers respectively expose a portion of the patterned circuit layers. The core layer is removed so as to expose an upper surface of each of the patterned circuit layers and a top surface of each of the patterned insulating layers. The upper surface of each of the patterned circuit layers is aligned with the top surface of each of the patterned insulating layers.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: June 27, 2017
    Assignee: Unimicron Technology Corp.
    Inventors: Chia-Chan Chang, Gwo-Chaur Chen, Yung-Tsai Chen
  • Publication number: 20170125337
    Abstract: A method for manufacturing a circuit structure is described as follows. Two patterned circuit layers are formed on a core layer. The patterned circuit layers are located on two opposite surfaces of the core layer. A patterned insulating layer is respectively formed on each of the patterned circuit layers. The patterned insulating layers respectively expose a portion of the patterned circuit layers. The core layer is removed so as to expose an upper surface of each of the patterned circuit layers and a top surface of each of the patterned insulating layers. The upper surface of each of the patterned circuit layers is aligned with the top surface of each of the patterned insulating layers.
    Type: Application
    Filed: November 3, 2015
    Publication date: May 4, 2017
    Inventors: Chia-Chan Chang, Gwo-Chaur Chen, Yung-Tsai Chen