Abstract: A method of making tungsten plug of integrated circuit is disclosed. The present invention is structured to deposit W metal by CVD onto the wafer which has Ti/TiN sputtered on as its top layer by employing quartz clamp rings of different sizes in two CVD chambers. The method can eliminate the Volcano phenomena in Ti, TiN or W metals and prevent peeling.

Abstract: In a wafer surface protection method, a protective film is formed on a front surface of a wafer before the wafer performs a potentially wafer process. The protective film is a non-adhesive layer. An adhesive tape is adhered onto the protective film before conducting the polluting process. After the polluting process is completed, the adhesive tape is removed along with the protective film. As a result, no adhesive residues remain on the surface of the wafer.

Abstract: In a wafer surface protection method, a protective film is formed on a front surface of a wafer before the wafer performs a potentially wafer process. The protective film is a non-adhesive layer. An adhesive tape is adhered onto the protective film before conducting the polluting process. After the polluting process is completed, the adhesive tape is removed along with the protective film. As a result, no adhesive residues remain on the surface of the wafer.

Abstract: A method of fabricating bonding pad structure for improving bonding pad surface quality. A substrate has a bonding pad thereon. A passivation is formed on the bonding pad to expose the bonding pad. A sacrificial layer is formed on the passivation and an opening is formed within the sacrificial layer to expose the bonding pad. A Cu/Al alloy is formed on the passivation to at least cover the bonding pad. The sacrificial layer and the Cu/Al alloy thereon are removed, such that the Cu/Al alloy remains on the bonding pad.

Abstract: The present invention relates to a method for actually measuring misalignment of a via. According to the invention, a via is formed by etching an inter metal dielectric (IMD) layer using a photoresist with a via pattern as a mask so that via pattern can be accurately transferred to the inter metal dielectric layer. Then a patterned metal interconnection line underlying the inter metal dielectric layer is etched using the patterned inter metal dielectric layer as a mask and followed by a process of stripping the inter metal dielectric layer. After that, an actual misalignment can be detected by measuring relative distance between the patterned metal interconnection line and the via thereon through Scanning Electron Microscopy (SEM), by which overlay specifications for OSI instrument can be verified and adjusted.

Abstract: A method of forming a CVD nitride (e.g., titanium nitride) film on a substrate. The as-deposited nitride film is treated by a plasma of a high power density (preferably between approximately 200 W and 300 W) for a prolonged duration of time (preferably between approximately 32 s and 52 s) to reduce the tendency of the resistance and thickness of the as-deposited film to change because of either time of exposure to atmosphere or subsequent processing steps.

Abstract: The present invention is a chemical vapor deposition of tungsten(W-CVD)process for growing low stress and void free interconnect. The method of this invention utilizes two steps W-CVD process by two chambers. The first step, filling tungsten metal completely in the contact hole, is performed in the first chamber. The second step, forming a tungsten layer for interconnect, is performed in the second chamber. Because of using two different chambers, the method of this invention can adjust the temperature of the process and the gas flow of the WF.sub.6 vapor of the process for different required the two steps. The second step of chemical vapor deposition of tungsten by adjusting the temperature and the gas flow has reduced greatly the stress of the second conductive layer. Moreover, the first step of chemical vapor deposition of tungsten by adjusting the temperature and the gas flow prevents voids in the contact hole or in the via hole.

Abstract: The present invention provides a method for stabilizing the crystal structure of a silicon substrate after an ion implantation process including the step of exposing the substrate to a temperature not higher than 200.degree. C. for a time period of not less than 10 seconds, and preferably to a temperature between about 100.degree. C. and about 200.degree. C. for a time period of between about 10 seconds and about 10,000 seconds.

Abstract: The present invention relates to a method of forming a barrier metal layer for a hot Al plug and its structure and more particularly to remarkably ameliorate the performance of a barrier metal layer preventing Al metal used as an interconnection layer from diffusing into a silicon substrate. A barrier metal layer according to the present invention is a stacked structure comprising a top layer of Tungsten (W) formed by a Chemical Vapor Deposition (CVD) method and a bottom layer of TiN. Then, a Al interconnection layer deposited at high temperature fills a plug and finishes a plug structure having advantages of low manufacturing cost and full prevention of Al diffusion.

Abstract: A clamp used in clamping semi-conductor wafers during processing operations permits ready release of the wafer and avoids adherence of the clamp to materials deposited onto the wafer which otherwise tend to stick the wafer to the clamp. Adhesion of the deposited materials to the clamp is avoided by providing the clamping surfaces of the clamp with a minimum surface roughness achieved by machining, grinding, etching or other techniques.

Abstract: The present invention discloses a method for reducing the reflectivity of a silicide layer. This invention utilizes a rapid thermal oxidation process to treat a tungsten silicide film in order to reduce the reflectivity of the tungsten silicide film. Thus, an anti-reflectivity layer is not required in the present invention. In addition simplify the present invention, a thin oxide layer is growth on the tungsten suicide layer during the rapid thermal oxidation process and the thin oxide layer serves as a hard mask in subsequent steps. In addition, because utilizing the rapid thermal process, the present invention can greatly reduce the resistance of the tungsten silicide in order to increase the speed of the devices.

Abstract: The present invention is a method of preventing defects and particles produced after tungsten etch back. The method utilizes the Ar plasma process, baking process, and D.I. water flushing with megasonic shacking to reduce a lot of defects and particles on the surface of a wafer. Thus, the present invention can prevent defects and particles produced after tungsten etch back.

Abstract: A two-step nucleation W-CVD process has been developed to suppress volcano formation which usually appears at W/TiN boundary. The process using different combination of spacing of W-CVD chamber between the shower head and heater and chamber pressure has been used to form an uniform nucleation layer (with uniformity of 5-6%). An uniform nucleation layer can prevent WF.sub.6 penetration during W-bulk deposition. Moreover, the reaction between WF.sub.6 and Ti can be suppressed. The formation of volcano at the clamp area around the wafer edge can be effectively reduced.