Patents by Inventor Yung-Wei Lu

Yung-Wei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194593
    Abstract: A method of forming a semiconductor device includes the following operations. A substrate is provided with an electric component. A composite dielectric layer is formed on the substrate and covers the electric component. An opening is formed through the composite dielectric layer. A directional etching process is performed to widen an upper portion of the opening. A metal feature is formed in the opening.
    Type: Application
    Filed: February 10, 2023
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Su, Yung-Hsu Wu, Hsin-Ping Chen, Chih Wei LU, Wei-Hao Liao, Hsi-Wen Tien, Cherng-Shiaw Tsai
  • Patent number: 12009256
    Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
  • Publication number: 20240186190
    Abstract: In an embodiment, a method includes: forming a first fin and a second fin over a semiconductor substrate; forming an isolation region between the first fin and the second fin, forming the isolation region comprising: depositing an oxide liner along the first fin, the second fin, and the semiconductor substrate, the oxide liner comprising a first upper portion and a first lower portion along the first fin, the first lower portion being between the first upper portion and the semiconductor substrate; thinning the oxide liner; depositing an insulation material over the oxide liner; and recessing the insulation material; and forming a gate structure over the first fin, the second fin, and the isolation region.
    Type: Application
    Filed: January 10, 2023
    Publication date: June 6, 2024
    Inventors: Cheng-I Lin, Cheng-Wei Chang, Ting-Hsiang Chang, Chih-Tang Peng, Yung-Cheng Lu
  • Publication number: 20240176093
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20070183543
    Abstract: This invention is to reveal a kind of noise isolation device designed on the power plug. In particular, a kind of power line communication noise isolation device. The purpose is to filter noises existing in the power line using environment through the use of a filter circuit and, at the same time of improving power line communication signal quality, the power line communication device could be connected to power plug together with other electrical appliances at the same time for the increase of convenience.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 9, 2007
    Inventor: Yung-Wei Lu
  • Patent number: 6979367
    Abstract: A method of improving surface planarity of a wafer. The method includes forming a first thin-film layer on the wafer using CVD in a first thin film deposition apparatus having at least one gas injector, relative to which the wafer has a first orientation, and forming a second thin-film layer on the wafer using CVD. The second deposition takes place in a second thin film deposition apparatus having at least one second gas injector arranged the same as that in the first thin film deposition apparatus, the wafer having a second orientation relative to the gas injector in the second thin film deposition apparatus. A first angle between the two orientations results in the second apparatus' injector distributing material in a different area from that of the first gas injector.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: December 27, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Ching Chan, Yun-Liang Ouyang, Yung-Wei Lu
  • Publication number: 20050037616
    Abstract: A method of improving surface planarity of a wafer. The method includes forming a first thin-film layer on the wafer using CVD in a first thin film deposition apparatus having at least one gas injector, relative to which the wafer has a first orientation, and forming a second thin-film layer on the wafer using CVD. The second deposition takes place in a second thin film deposition apparatus having at least one second gas injector arranged the same as that in the first thin film deposition apparatus, the wafer having a second orientation relative to the gas injector in the second thin film deposition apparatus. A first angle between the two orientations results in the second apparatus' injector distributing material in a different area from that of the first gas injector.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 17, 2005
    Inventors: Chien-Ching Chan, Yun-Liang Ouyang, Yung-Wei Lu