Abstract: A vertical semiconductor transistor is provided that includes: a source region, a drain region, and a body region formed in a semiconductor substrate; wherein the source region and the drain region are doped with a first type dopant; wherein the body region is doped with a second type dopant; and wherein the second type dopant has a doping profile within the body region that varies with distance from the source region.

Abstract: A system includes a voltage source, a current source, and a testing station. The testing system is arranged to mechanically and electrically connect to multiple head gimbal assemblies (HGAs) simultaneously, and the testing station includes conductors for electrically coupling to conductive pads of the HGAs. The system further includes memory containing instructions for causing a computing device to connect either the voltage source or the current source to the conductors corresponding to each of the HGAs to be connected to the testing station.

Abstract: Embodiments provide efficient, robust, and accurate programmatic prediction of optimized TCAD simulator system settings for future simulation executions to be performed by a TCAD simulation system.

Abstract: A roller shutter may include a rotatable drum; a shutter curtain including a series of three or more elongate slats pivotally interlocked in a longitudinal-edge-to-longitudinal-edge arrangement and arranged parallel to the rotatable drum, wherein a first and second longitudinal end portions of each elongate slat may be respectively aligned to form a first side border and a second side border, respectively, of the shutter curtain, wherein the first and second longitudinal end portions of each elongate slat may be respectively provided with at least one eyelet-structure which protrudes therefrom, whereby a first and second rows of eyelet-structures are formed along the first and second side borders; and at least a first cord and a second cord respectively strung loosely through all eyelet-structures of respective row of eyelet-structures, and each cord may be configured to confine all eyelet-structures of the respective row of eyelet-structures within a length of each cord.

Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a physically unclonable function (PUF) device includes a crystalline substrate and a stack of crystalline layers on top. The stack is grown epitaxially such that lattice mismatch causes threading dislocations from the substrate to the top surface of the stack. Diodes are formed on the top surface by forming anode material on the top surface of the stack, thereby forming a diode junction with a cathode region below. A diode which includes a threading dislocation has a higher leakage current than one that does not. Circuitry connected to the diodes interrogates the array and outputs binary values indicating, for each of the diodes, whether the diode includes a threading dislocation. Such binary values can be used as the PUF of the chip. This Abstract is not intended to limit the scope of the claims.

Abstract: A system includes a voltage source, a current source, and a testing station. The testing system is arranged to mechanically and electrically connect to multiple head gimbal assemblies (HGAs) simultaneously, and the testing station includes conductors for electrically coupling to conductive pads of the HGAs. The system further includes memory containing instructions for causing a computing device to connect either the voltage source or the current source to the conductors corresponding to each of the HGAs to be connected to the testing station.

Abstract: The present invention provides device for generating magnetic field of calibration and built-in self-calibration (BISC) magnetic sensor and calibration method, in which a novelty structure utilized for generating a uniform, predetermined magnitude, and three-dimensional orthogonal or approximately orthogonal magnetic field of calibration is arranged in the magnetic sensor such that the magnetic sensor can perform BISC function for obtaining a calibrating information with respect to the magnetic field of calibration anytime and anywhere. The magnetic sensor can be arranged in the application device for measuring magnetic field under the real environment where the magnetic sensor is located and the calibrating information are utilized for calibrating the measuring result thereby improving and advancing the accuracy of measuring three-dimensional magnetic field.

Abstract: A slat assembly may include a slat having a first and second receiving portion. The first and second receiving portions being a pair of bent portions forming an acute angle. The slat assembly may further include an insulation layer lined on the slat. The slat assembly may further include a retaining mechanism disposed on the insulation layer to press a first portion of the insulation layer into the first receiving portion of the slat and to press a second portion of the insulation layer into the second receiving portion of the slat such that the retaining mechanism may cooperate with the first and second receiving portions to hold the insulation layer between the retaining mechanism and the slat without puncturing or penetrating the insulation layer with fasteners. A roller shutter including the slat assembly. A method of manufacturing a slat assembly and a method of manufacturing a roller shutter.

Abstract: A roller shutter may include a rotatable drum; a shutter curtain including a series of three or more elongate slats pivotally interlocked in a longitudinal-edge-to-longitudinal-edge arrangement and arranged parallel to the rotatable drum, wherein a first and second longitudinal end portions of each elongate slat may be respectively aligned to form a first side border and a second side border, respectively, of the shutter curtain, wherein the first and second longitudinal end portions of each elongate slat may be respectively provided with at least one eyelet-structure which protrudes therefrom, whereby a first and second rows of eyelet-structures are formed along the first and second side borders; and at least a first cord and a second cord respectively strung loosely through all eyelet-structures of respective row of eyelet-structures, and each cord may be configured to confine all eyelet-structures of the respective row of eyelet-structures within a length of each cord.

Abstract: A slat assembly may include a slat having a first and second receiving portion. The first and second receiving portions being a pair of bent portions forming an acute angle. The slat assembly may further include an insulation layer lined on the slat. The slat assembly may further include a retaining mechanism disposed on the insulation layer to press a first portion of the insulation layer into the first receiving portion of the slat and to press a second portion of the insulation layer into the second receiving portion of the slat such that the retaining mechanism may cooperate with the first and second receiving portions to hold the insulation layer between the retaining mechanism and the slat without puncturing or penetrating the insulation layer with fasteners. A roller shutter including the slat assembly. A method of manufacturing a slat assembly and a method of manufacturing a roller shutter.

Abstract: The present invention provides device for generating magnetic field of calibration and built-in self-calibration (BISC) magnetic sensor and calibration method, in which a novelty structure utilized for generating a uniform, predetermined magnitude, and three-dimensional orthogonal or approximately orthogonal magnetic field of calibration is arranged in the magnetic sensor such that the magnetic sensor can perform BISC function for obtaining a calibrating information with respect to the magnetic field of calibration anytime and anywhere. The magnetic sensor can be arranged in the application device for measuring magnetic field under the real environment where the magnetic sensor is located and the calibrating information are utilized for calibrating the measuring result thereby improving and advancing the accuracy of measuring three-dimensional magnetic field.

Abstract: Roughly described, an integrated circuit device includes a semiconductor having an overall length. In successively adjacent longitudinal sequence, the semiconductor includes first, second and third lengths all having a same first conductivity type. One end of the longitudinal sequence (the end adjacent to the first length) can be referred to a source end of the sequence, and the other end (adjacent to the third length) can be referred to as a drain end. Overlying the second length is a first gate conductor, which defines a first body region. Overlying a cascode portion of the third length is a second gate conductor, which defines a second body region. The second gate conductor preferably is longitudinally continuous with the first gate conductor, but if not, then the two are connected together by other conductors. The first body region is recessed relative to the first and third lengths of the semiconductor.

Abstract: An improved local modeling function for estimating band-to-band tunneling currents RBBT in nanodevices and other low-voltage circuit elements during TCAD simulation, the model being represented by the equation: R B ? B ? T = - B ? ? F ? ? = exp ? ( - F 0 ? F ? ) ? g where terms B, F, F0 and ? correspond to conventional terms used in Hurkx-based equations, and the term g is an exponential factor determined by the equation: g = ( F - F 1 F 1 ) 1 . 5 where the term F1 is the built-in electric field at a selected cell/point determined by the equation: F 1 = max ? ( F ˜ 1 , C ? 2 ? q ? E g ? N n ? e ? t ? ) where {tilde over (F)}1 is the built-in electric field at zero bias, q is fundamental electronic charge, C is a fitting parameter, Eg is bandgap, Nnet is doping concentration, and E is dielectric constant.

Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.

Abstract: The independent claims of this patent signify a concise description of the embodiments. Disclosed is technology for reducing transistor degradations by annealing through heat generated by anti-punch-through implants of the transistors. A first and second electrically conductive pillars are disposed on top a well hosting the transistors. A voltage applied across the first and second pillars enable the anti-punch-through implants to generate heat for the annealing process.

Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed herein is a normally-off, gallium oxide field-effect transistor. The field-effect transistor comprises a source, a source spacer, a first channel region, a second channel region, a drain spacer, and a drain. The source, the source spacer, the first channel region, the second channel region, the drain spacer, and the drain are of a first conductivity type. All the regions have the same type of doping. The field-effect transistor further includes a gate dielectric over the channel body and a gate over the gate dielectric. The first channel region has a cross-sectional area that is smaller than the second channel region.

Abstract: Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.

Abstract: A torsion spring counter balancing mechanism for a stacking panel shutter door includes one or more torsion springs one end of the or each torsion spring is fixable to a drive transmission shaft of the stacking panel shutter door, the drive transmission shaft being adapted to raise and lower the or each shutter of the stacking panel shutter door; and the other end of the or each torsion spring is fixable to a separate rotatable member of the stacking panel shutter door; whereby the mechanism is provided with means adapted to enable both the drive transmission shaft and the rotatable member to rotate, during opening and closing of the stacking panel shutter door, in such a manner as to cause respective ends of the or each torsion spring to travel at different speeds during the opening and closing sequence, which permits to keep the same size motor when panel numbers are varied.

Abstract: Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.

Abstract: Fire can spread extremely quickly within structures. To prevent this, fire doors or fire shutters are usually installed. However, security aspects of such doors or shutters are not renown. An attempt to alleviate this problem may be provided by an insulated fire panel shutter including a guide, adapted to receive a shutter and having one or more retractable members moveable between a retracted and extended position; a shutter, moveable between an open and closed position and formed from a plurality of panels each of which is moveable between a stowed and deployed position; their arrangement being such that as the guide receives the shutter during shutter closure, the panel arrangement alters from a stowed side by side relationship to a deployed stacked end to end relationship.