Patents by Inventor Yung-Yu Wang

Yung-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384521
    Abstract: Structures and formation methods of a semiconductor structure are provided. The semiconductor structure includes an insulating layer covering a device region and an alignment mark region of a semiconductor substrate. A conductive feature is formed in the insulating layer and corresponds to the device region. An alignment mark structure is formed in the first insulating layer and corresponds to the alignment mark region. The alignment mark structure includes a first conductive layer, a second conductive layer covering the first conductive layer, and a first magnetic tunnel junction (MTJ) stack layer covering the second conductive layer. The first conductive layer and the conductive feature are made of the same material.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Inventors: Wei-De HO, Lan-Hsin CHIANG, Chien-Hua HUANG, Chung-Te LIN, Yung-Yu WANG, Sheng-Yuan CHANG, Kai-Chieh LIANG
  • Patent number: 10026838
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ta Wu, Yung-Yu Wang, Yung-Hsiang Chan, Chia-Ying Tsai, Ting-Chun Wang
  • Publication number: 20170250280
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Cheng-Ta Wu, Yung-Yu Wang, Yung-Hsiang Chan, Chia-Ying Tsai, Ting-Chun Wang