Patents by Inventor Yung-Yu Wang

Yung-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145911
    Abstract: An antenna correcting system is provided. The antenna correction system compares amplitudes of antenna signals that are emitted or received respectively by a plurality of antenna units with each other to select one of the amplitudes as target amplitude. The antenna correction system corrects the amplitude of each of the antenna signals according to the target amplitude. As a result, the amplitudes of the antenna signals are the same as each other or approximate to each other. After the amplitudes of the antenna signals are corrected, the antenna correction system compares phases of the antenna signals with each other to select one of the phases as a target phase. The antenna correction system corrects the phase of each of the antenna signals according to the target phase. As a result, the phases of the antenna signals are the same as each other or approximate to each other.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 2, 2024
    Inventors: YUNG-TAI HSU, CHUN-HENG CHAO, YEN-WEI WANG, BO-YU ZHU
  • Patent number: 11955154
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • Patent number: 11942130
    Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Jhong Chen, Yi-Ting Wu, Jen-Yu Wang, Cheng-Tung Huang, Po-Chun Yang, Yung-Ching Hsieh
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240088056
    Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Inventors: Jhih-Yu Wang, Yung-Chi Chu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20220384521
    Abstract: Structures and formation methods of a semiconductor structure are provided. The semiconductor structure includes an insulating layer covering a device region and an alignment mark region of a semiconductor substrate. A conductive feature is formed in the insulating layer and corresponds to the device region. An alignment mark structure is formed in the first insulating layer and corresponds to the alignment mark region. The alignment mark structure includes a first conductive layer, a second conductive layer covering the first conductive layer, and a first magnetic tunnel junction (MTJ) stack layer covering the second conductive layer. The first conductive layer and the conductive feature are made of the same material.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Inventors: Wei-De HO, Lan-Hsin CHIANG, Chien-Hua HUANG, Chung-Te LIN, Yung-Yu WANG, Sheng-Yuan CHANG, Kai-Chieh LIANG
  • Patent number: 10026838
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: July 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ta Wu, Yung-Yu Wang, Yung-Hsiang Chan, Chia-Ying Tsai, Ting-Chun Wang
  • Publication number: 20170250280
    Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Cheng-Ta Wu, Yung-Yu Wang, Yung-Hsiang Chan, Chia-Ying Tsai, Ting-Chun Wang