Patents by Inventor Yung-Yu Wu

Yung-Yu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120163798
    Abstract: In a controlling circuit, a photo coupler is used for isolating noises, and a general purpose amplifier is used for adjusting a gain, so that a logic tester may test analog signals in cooperation with relays having different specifications and operating voltage level differences in an analog measurement module. A shift register of each controlling circuit of a controlling module also transmits a test data signal to a next stage controlling circuit, so that a logic tester may simultaneously output a plurality of bits to multiple controlling circuits and multiple analog measurement modules by using merely one I/O port.
    Type: Application
    Filed: June 24, 2011
    Publication date: June 28, 2012
    Inventors: Yang-Han Lee, Yung-Yu Wu, Huei-Huang Chen
  • Publication number: 20120126856
    Abstract: In an adjustable voltage examining module, while a logic tester issues an input signal to an audio module under test, upper/low-threshold reference signals are simultaneously issued to an adjustable voltage comparing circuit. While the adjustable voltage comparing circuit receives a signal under test returned by the to-be-examined audio module after a while, the adjustable voltage comparing circuit loads both an high-threshold reference voltage and a low-threshold reference voltage respectively indicated by the reference upper/low-threshold signal so as to compare both the upper and low-threshold reference voltages with the signal under test. Therefore, while the signal under test is examined to acquire a voltage level between voltage levels of the upper and low-threshold reference signals, precise operations of the audio module under test are assured, and time wasted by continuously-issued interrupt is saved.
    Type: Application
    Filed: May 24, 2011
    Publication date: May 24, 2012
    Inventors: Yang-Han Lee, Yung-Yu Wu
  • Patent number: 8148996
    Abstract: The invention discloses a circuit testing apparatus for testing a device under testing. The circuit testing apparatus includes a logic tester and a signal-measuring module. The logic tester is coupled to the device under testing for providing a testing signal and a trigger signal, and then determining a testing result for the device under testing according to a digital measuring result. The signal-measuring module coupled to the device under testing and the logic tester, is utilized for measuring a DC signal generated by the device under testing according to the testing signal after receiving the trigger signal, and generating the digital measuring result.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: April 3, 2012
    Assignee: Princeton Technology Corporation
    Inventors: Cheng-Yung Teng, Hung-Wei Chen, Yung-Yu Wu
  • Patent number: 8099659
    Abstract: The invention provides a logic tester. In one embodiment, the logic tester is coupled to a plurality of tested devices, and includes a function generator and a pattern comparator. The function generator generates an initial code sequence as an input signal of the tested devices to fix output signals of the tested devices to a first value, and then generates a functional code sequence as the input signal of the tested devices to trigger the output signals of the tested devices to change from the first value to a second value. The pattern comparator converts the output signals of the tested devices to a plurality of bitstreams after the functional code sequence is generated, calculates numbers of bits corresponding to the first value in the bitstreams, estimates delay periods of the tested devices according to the numbers of bits, and outputs the delay periods of the tested devices.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: January 17, 2012
    Assignee: Princeton Technology Corporation
    Inventors: Yung-Yu Wu, Huei-Huang Chen
  • Patent number: 8044675
    Abstract: A testing apparatus includes a public test board, a single DUT (device under test) test board and a holder. The public test board includes a plurality of public test channel sets each having a plurality of public signal terminals for receiving test signals. On the single DUT test board, a plurality first signal terminals are arranged according to the pin layout of a DUT, a plurality second signal terminals are arranged according to the terminal layout of a public channel set, and a plurality traces are arranged for electrically connecting corresponding first and second signal terminals. The holder can connect the pins of the DUT to corresponding first signal terminals.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: October 25, 2011
    Assignee: Princeton Technology Corporation
    Inventors: Yung-Yu Wu, Huei-Huang Chen, Wei-Fen Chiang
  • Patent number: 7830163
    Abstract: The invention discloses a testing circuit board for placing a device under test and further testing the device under test according to a plurality of testing signals generated by a tester. The testing circuit board includes a circuit board and a plurality of sets of sockets. The circuit board includes a plurality of connecting holes. The plurality of sets of sockets are located on a plurality of connecting holes and electrically connects to the device under test via a plurality of connecting interfaces for transferring the plurality of testing signals to test the device under test.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: November 9, 2010
    Assignee: Princeton Technology Corporation
    Inventors: Cheng-Yung Teng, Li-Jieu Hsu, Wei-Fen Chiang, Yung-Yu Wu, Hung-Wei Chen, Huei-Huang Chen
  • Publication number: 20100271041
    Abstract: A testing apparatus includes a public test board, a single DUT (device under test) test board and a holder. The public test board includes a plurality of public test channel sets each having a plurality of public signal terminals for receiving test signals. On the single DUT test board, a plurality first signal terminals are arranged according to the pin layout of a DUT, a plurality second signal terminals are arranged according to the terminal layout of a public channel set, and a plurality traces are arranged for electrically connecting corresponding first and second signal terminals. The holder can connect the pins of the DUT to corresponding first signal terminals.
    Type: Application
    Filed: April 26, 2010
    Publication date: October 28, 2010
    Inventors: Yung-Yu Wu, Huei-Huang Chen, Wei-Fen Chiang
  • Publication number: 20100153800
    Abstract: The invention provides a logic tester. In one embodiment, the logic tester is coupled to a plurality of tested devices, and includes a function generator and a pattern comparator. The function generator generates an initial code sequence as an input signal of the tested devices to fix output signals of the tested devices to a first value, and then generates a functional code sequence as the input signal of the tested devices to trigger the output signals of the tested devices to change from the first value to a second value. The pattern comparator converts the output signals of the tested devices to a plurality of bitstreams after the functional code sequence is generated, calculates numbers of bits corresponding to the first value in the bitstreams, estimates delay periods of the tested devices according to the numbers of bits, and outputs the delay periods of the tested devices.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 17, 2010
    Inventors: Yung-Yu Wu, Huei-Huang Chen
  • Publication number: 20090108859
    Abstract: The invention discloses a testing circuit board for placing a device under test and further testing the device under test according to a plurality of testing signals generated by a tester. The testing circuit board includes a circuit board and a plurality of sets of sockets. The circuit board includes a plurality of connecting holes. The plurality of sets of sockets are located on a plurality of connecting holes and electrically connects to the device under test via a plurality of connecting interfaces for transferring the plurality of testing signals to test the device under test.
    Type: Application
    Filed: October 7, 2008
    Publication date: April 30, 2009
    Inventors: Cheng-Yung TENG, Li-Jieu HSU, Wei-Fen CHIANG, Yung-Yu WU, Hung-Wei CHEN, Huei-Huang CHEN
  • Publication number: 20080191730
    Abstract: The invention discloses a circuit testing apparatus for testing a device under testing. The circuit testing apparatus includes a logic tester and a signal-measuring module. The logic tester is coupled to the device under testing for providing a testing signal and a trigger signal, and then determining a testing result for the device under testing according to a digital measuring result. The signal-measuring module coupled to the device under testing and the logic tester, is utilized for measuring a DC signal generated by the device under testing according to the testing signal after receiving the trigger signal, and generating the digital measuring result.
    Type: Application
    Filed: May 9, 2007
    Publication date: August 14, 2008
    Inventors: Cheng-Yung Teng, Hung-Wei Chen, Yung-Yu Wu
  • Patent number: 6942515
    Abstract: A connector for power or data transmission includes terminals arranged at front and rear sides of a main body thereof. Each of the terminals has a middle portion embedded in an injection-molded plastic material of the main body, a conducting head slightly upward exposed from the main body, and a soldering tail flatly attached to a bottom of the main body. The conducting head and the soldering tail are axially offset from the middle portion in two opposite directions, so that conducting heads of terminals at the front or rear side of the main body and soldering tails extended from terminals at the other side alternate at each side of the main body. A cover is turnably closed to a top of the main body to press and electrically connect an inserted card to the conducting heads of the connector.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: September 13, 2005
    Inventor: Yung-Yu Wu