Patents by Inventor Yung-Yu Yang

Yung-Yu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250053161
    Abstract: A manufacturing control method is applied to a computer system comprising a processor, a storage device, and a display device. The manufacturing control method includes: dividing a plurality of outlier-filtered data into a plurality of data subgroups based on a group division reference value; calculating a plurality of standard deviations for each of these data subgroups; calculating a warning line upper limit and a warning line lower limit based on the group division reference value, a predetermined multiple, and the standard deviations; adjusting either the warning line upper limit or the warning line lower limit based on the predetermined multiple and the standard deviations; and when a sensing data exceeds the warning line upper limit or the warning line lower limit, the computing system triggers a warning signal.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 13, 2025
    Inventors: Yung-Yu YANG, Chih-Kuan CHANG, Chung-Chih HUNG, Yu-Hsien TSAI, Chen-Hui HUANG
  • Publication number: 20240176335
    Abstract: A fault detection method, includes the following steps. A target sequence is received, the target sequence includes several data. A first moving average operation is performed on the target sequence to establish a first moving average sequence. A second moving average operation is performed on the target sequence to establish a second moving average sequence. A difference operation between the first moving average sequence and the second moving average sequence is performed to obtain a difference sequence, the difference sequence includes several difference values. An upper limit value is set. When one of the difference values is greater than the upper limit value, the target sequence is determines as abnormal.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 30, 2024
    Inventors: Yung-Yu Yang, Kang-Ping Li, Chih-Kuan Chang, Chung-Chih Hung, Chen-Hui Huang, Nai-Ying Lo, Shih-Wei Huang
  • Publication number: 20240004374
    Abstract: A fault detection method comprises the following steps. Receiving a first original sequence comprising a plurality of first data. Receiving a second original sequence comprising a plurality of second data. Aligning the first original sequence with the second original sequence according to trends of value changing of the first data and the second data. Performing an average operation on the aligned first original sequence and second original sequence to establish a standard sequence. Performing a difference operation between the first original sequence and the standard sequence to obtain a first total difference value. Performing a difference operation between the second original sequence and the standard sequence to obtain a second total difference value. When the first total difference value and/or the second total difference value is greater than an upper limit value, determining that the first original sequence and/or the second total difference value is abnormal.
    Type: Application
    Filed: July 27, 2022
    Publication date: January 4, 2024
    Inventors: Yung-Yu YANG, Kang-Ping LI, Chih-Kuan CHANG, Chung-Chih HUNG, Chen-Hui HUANG, Nai-Ying LO, Shih-Wei HUANG
  • Patent number: 11821847
    Abstract: A wafer backside defect detection method and a wafer backside defect detection apparatus are provided. The wafer backside defect detection method includes the following steps. A peripheral edge area of a wafer backside image that at least one notch is located is cropped off. Adjacent white pixels on the wafer backside image are connected to obtain a plurality of abnormal regions. If a total area of top N of the abnormal regions is more than 10% of an area of the wafer, it is deemed that the wafer has a roughness defect. N is a natural number. If the total area of the top N of the abnormal regions is less than 1% of the area of the wafer and a largest abnormal region of the abnormal regions is longer than a predetermined length, it is deemed that the wafer has a scratch defect.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: November 21, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Hsien Chen, Chia-Feng Hsiao, Chung-Hsuan Wu, Chen-Hui Huang, Nai-Ying Lo, En-Wei Tsui, Yung-Yu Yang, Chen-Hsuan Hung
  • Patent number: 11644427
    Abstract: An automatic detection method and an automatic detection system for detecting any crack on wafer edges are provided. The automatic detection method includes the following steps. Several wafer images of several wafers are obtained. The wafer images are integrated to create a templet image. Each of the wafer images is compared with the templet image to obtain a differential image. Each of the differential images is binarized. Each of the differential images which are binarized is de-noised. Whether each of the differential images has an edge crack is detected according to pattern of each of the differential images which are de-noised.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 9, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Feng Hsiao, Chung-Hsuan Wu, Shuo-Yu Chen, Nai-Ying Lo, Yi-Hui Tseng, Chen-Hui Huang, Yung-Yu Yang, Tzu-Ping Kao
  • Publication number: 20230024259
    Abstract: A wafer backside defect detection method and a wafer backside defect detection apparatus are provided. The wafer backside defect detection method includes the following steps. A peripheral edge area of a wafer backside image that at least one notch is located is cropped off. Adjacent white pixels on the wafer backside image are connected to obtain a plurality of abnormal regions. If a total area of top N of the abnormal regions is more than 10% of an area of the wafer, it is deemed that the wafer has a roughness defect. N is a natural number. If the total area of the top N of the abnormal regions is less than 1% of the area of the wafer and a largest abnormal region of the abnormal regions is longer than a predetermined length, it is deemed that the wafer has a scratch defect.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 26, 2023
    Inventors: Cheng-Hsien CHEN, Chia-Feng HSIAO, Chung-Hsuan WU, Chen-Hui HUANG, Nai-Ying LO, En-Wei TSUI, Yung-Yu YANG, Chen-Hsuan HUNG
  • Publication number: 20220128485
    Abstract: An automatic detection method and an automatic detection system for detecting any crack on wafer edges are provided. The automatic detection method includes the following steps. Several wafer images of several wafers are obtained. The wafer images are integrated to create a templet image. Each of the wafer images is compared with the templet image to obtain a differential image. Each of the differential images is binarized. Each of the differential images which are binarized is de-noised. Whether each of the differential images has an edge crack is detected according to pattern of each of the differential images which are de-noised.
    Type: Application
    Filed: November 23, 2020
    Publication date: April 28, 2022
    Inventors: Chia-Feng HSIAO, Chung-Hsuan WU, Shuo-Yu CHEN, Nai-Ying LO, Yi-Hui TSENG, Chen-Hui HUANG, Yung-Yu YANG, Tzu-Ping KAO
  • Patent number: 10606253
    Abstract: A method of monitoring a processing system for processing a substrate is provided. The method includes the following steps: acquiring data from the processing system for a plurality of parameters, the data including a plurality of data values; grouping the parameters into a plurality of sub-groups, each of the sub-groups including a plurality of correlated parameters; constructing a principle components analysis (PCA) model from the data values for the correlated parameters in a first one of the sub-groups, including normalizing the data values in the first one of the sub-groups with a first weighting factor and a second weighting factor, wherein the first weighting factor is different from the second weighting factor; and determining a statistical quantity using the PCA model.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lian-Hua Shih, Chia-Chi Chang, Li-Ting Lin, Ching-Hsing Hsieh, Feng-Chi Chung, Meng-Chih Chang, Ming-Tung Wang, Chiu-Ping Chang, Yung-Yu Yang
  • Publication number: 20180224817
    Abstract: A method of monitoring a processing system for processing a substrate is provided. The method includes the following steps: acquiring data from the processing system for a plurality of parameters, the data including a plurality of data values; grouping the parameters into a plurality of sub-groups, each of the sub-groups including a plurality of correlated parameters; constructing a principle components analysis (PCA) model from the data values for the correlated parameters in a first one of the sub-groups, including normalizing the data values in the first one of the sub-groups with a first weighting factor and a second weighting factor, wherein the first weighting factor is different from the second weighting factor; and determining a statistical quantity using the PCA model.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 9, 2018
    Inventors: Lian-Hua Shih, Chia-Chi Chang, Li-Ting Lin, Ching-Hsing Hsieh, Feng-Chi Chung, Meng-Chih Chang, Ming-Tung Wang, Chiu-Ping Chang, Yung-Yu Yang