Patents by Inventor Yung-Chieh Fan

Yung-Chieh Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 6509243
    Abstract: In a method for integrating a high-voltage device and a low-voltage device, a substrate includes a first isolation region separating a high-voltage device region and a low-voltage device region, a second isolation region formed in a scribe region, and a patterned insulating layer that exposes the first and second isolation regions. A patterned photoresist, formed over the substrate, exposes a portion of the patterned insulating layer in the high-voltage device region and a portion of the second isolation region in the scribe region. A doped region and a trench are respectively formed in the substrate under the exposed portion of the patterned insulating layer and in the exposed portion of the second isolation region. The patterned photoresist and the patterned insulating layer are subsequently removed. First and second gate structures are respectively formed in the high-voltage and low-voltage device regions by using the trench as an alignment mark.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: January 21, 2003
    Assignee: United Microelectronics Corp.
    Inventor: Yung-Chieh Fan
  • Publication number: 20020197812
    Abstract: A method for integrating a high-voltage device and a low-voltage device. A substrate having a patterned insulating layer is provided. A first isolation region and a second isolation region are formed on the substrate exposed by the patterned insulating layer. The second isolation region is located on the substrate in the scribe region. A patterned photoresist is formed over the substrate to expose a portion of the patterned insulating layer in the high-voltage device region and a portion of the second isolation region in the scribe region. A doped region is formed in the substrate under the portion of the patterned insulating layer exposed by the patterned photoresist. A trench is formed in the second isolation region exposed by the patterned photoresist in the scribe region. The patterned photoresist and the patterned insulating layer are removed in sequence. A drive-in process is performed to transform the doped region into a grade region.
    Type: Application
    Filed: June 25, 2001
    Publication date: December 26, 2002
    Applicant: Unite Microelectronics Corp.
    Inventor: Yung-Chieh Fan
  • Patent number: 6153446
    Abstract: A method for forming a metallic reflecting layer in a semiconductor photodiode including a CMOS photodiode to enhance the sensitivity by filling a trench formed in the isolation next to the depletion region of the semiconductor photodiode with high reflectivity metal. The metal filled in the trench is used as a metallic reflecting layer to increase the number of photons reaching the depletion region by reflecting part of the aslope incident photons. An insulator is formed on the top of the metallic reflecting layer to electrically insulate the metallic reflecting layer from other conducting device formed by the follow-up process.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: November 28, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Ming-I Chen, Yung-Chieh Fan
  • Patent number: 6118142
    Abstract: A CMOS sensor structure and method of manufacture that includes the fabrication of a special shallow trench isolation structure. Besides isolating the active region for forming the CMOS sensor device, the shallow trench isolation structure has a special reflective plug embedded inside capable of reflecting incoming light onto the sensitive region of the CMOS sensor. Hence, the interactive length of incoming light with the light sensitive region can be increased, thereby increasing the contrast ratio and light sensitivity of the CMOS sensor.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: September 12, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Ming-I Chen, Yung-Chieh Fan
  • Patent number: 5872066
    Abstract: A method of forming an inter-metal dielectric layer using hydrogen silsesquoxane (HSQ) as one of the dielectric layers. HSQ is a highly fluidic material that has a high gap-filling capacity. Therefore, the desired thickness and uniformity can be obtained in a single coating operation. Furthermore, when the HSQ layer is cured in an atmosphere of gaseous nitrogen, the HSQ layer is able to attain a high degree of planarity. Consequently, there is no need to planarize the dielectric layer before carrying out subsequent operations.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: February 16, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yu Fang, Kuo-Liang Huang, Ching-Gji Hsu, Yung-Chieh Fan