Abstract: A method for fabricating a semiconductor product includes forming a dielectric layer over a top level metallization layer of a semiconductor process wafer. The dielectric layer is patterned using a grayscale mask process to define a contact pad opening in the dielectric layer, thereby producing a patterned dielectric layer in which the contact pad opening is aligned to a contact pad defined in the top level metallization layer. A metal layer is deposited over the patterned dielectric layer, including within the contact pad opening. A portion of the metal layer is removed by a chemical mechanical polishing (CMP) process, with a remaining portion of the metal layer having a sloped sidewall.

Abstract: A method of etching a metal containing layer including a metal including material includes providing a substrate including a top semiconductor surface having the metal containing layer thereon. A photoresist pattern is formed from a photoresist layer on the metal containing layer including forming sloped edge regions of the photoresist layer, wherein the sloped edge regions have an average angle over a full length of the sloped edge regions of from ten (10) to fifty (50) degrees. The metal containing layer is dry etched using the photoresist pattern, wherein the sloped edge regions of the photoresist layer reduce deposition and growth of an etch byproduct including the metal including material into sidewalls of the photoresist layer (metal/polymer sidewall defect) as compared to a conventional vertical (or near-vertical) edge of the photoresist layer.

Abstract: A method of etching a metal containing layer including a metal including material includes providing a substrate including a top semiconductor surface having the metal containing layer thereon. A photoresist pattern is formed from a photoresist layer on the metal containing layer including forming sloped edge regions of the photoresist layer, wherein the sloped edge regions have an average angle over a full length of the sloped edge regions of from ten (10) to fifty (50) degrees. The metal containing layer is dry etched using the photoresist pattern, wherein the sloped edge regions of the photoresist layer reduce deposition and growth of an etch byproduct including the metal including material into sidewalls of the photoresist layer (metal/polymer sidewall defect) as compared to a conventional vertical (or near-vertical) edge of the photoresist layer.

Abstract: A shallow trench isolation (STI) test pattern comprising a plurality of test structures. Each of the test structures comprise at least two lines comprising a predefined line length, line width, and gap between the lines. At least one of the line length, line width and gap are different between each of the plurality of the test structures.

Abstract: One aspect of the invention relates to a method of manufacturing a semiconductor device in which an alignment mark is formed by a plurality of adjacent filled trenches. A processing tool detects the trenches as though they were a single filled trench of larger dimension. When the trenches are metal filled, the metal is more easily protected from oxidation than when the metal is formed into a single large trench, an effect that is pronounced when the trenches are filled with tungsten. Another aspect of the invention relates to an alignment mark formed by a plurality of tungsten filled trenches. The alignment mark can be used to align the pattern for an FeRAM capacitor stack to underlying tungsten contacts.