Patents by Inventor Yung Woo Lee
Yung Woo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11949881Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.Type: GrantFiled: April 1, 2021Date of Patent: April 2, 2024Assignees: Electronics and Telecommunications Research Institute, Kwangwoon University Research Institute for Industry Cooperation, Industry-Academia Cooperation Group of Sejong UniversityInventors: Se-Yoon Jeong, Hae-Chul Choi, Jeong-Il Seo, Seung-Kwon Beack, In-Seon Jang, Jae-Gon Kim, Kyung-Ae Moon, Dae-Young Jang, Jin-Woo Hong, Jin-Woong Kim, Yung-Lyul Lee, Dong-Gyu Sim, Seoung-Jun Oh, Chang-Beom Ahn, Dae-Yeon Kim, Dong-Kyun Kim
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Publication number: 20240098311Abstract: The present invention relates to an image encoding/decoding method and apparatus. An image encoding method according to the present invention may comprise generating a transform block by performing at least one of transform and quantization; grouping at least one coefficient included in the transform block into at least one coefficient group (CG); scanning at least one coefficient included in the coefficient group; and encoding the at least one coefficient.Type: ApplicationFiled: November 20, 2023Publication date: March 21, 2024Applicants: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, INDUSTRY ACADEMY COOPERATION FOUNDATION OF SEJONG UNIVERSITYInventors: Sung Chang LIM, Jung Won KANG, Hyun Suk KO, Jin Ho LEE, Dong San JUN, Ha Hyun LEE, Seung Hyun CHO, Hui Yong KIM, Jin Soo CHOI, Yung Lyul LEE, Jun Woo CHOI
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Patent number: 11930179Abstract: An image encoding/decoding method is provided. An image decoding method of the present invention may comprise deriving an intra-prediction mode of a current luma block, deriving an intra-prediction mode of a current chroma block based on the intra-prediction mode of the current luma block, generating a prediction block of the current chroma block based on the intra-prediction mode of the current chroma block, and the deriving of an intra-prediction mode of a current chroma block may comprise determining whether or not CCLM (Cross-Component Linear Mode) can be performed for the current chroma block.Type: GrantFiled: December 27, 2019Date of Patent: March 12, 2024Assignees: Electronics and Telecommunications Research Institute, INDUSTRY ACADEMY COOPERATION FOUNDATION OF SEJONG UNI, CHIPS & MEDIA, INC, INDUSTRY-UNIVERSITY COOPERATION FOUNDATION KOREA AEROSPACE UNIVERSITYInventors: Sung Chang Lim, Jung Won Kang, Ha Hyun Lee, Jin Ho Lee, Hui Yong Kim, Yung Lyul Lee, Ji Yeon Jung, Nam Uk Kim, Myung Jun Kim, Yang Woo Kim, Dae Yeon Kim, Jae Gon Kim, Do Hyeon Park
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Publication number: 20230257257Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.Type: ApplicationFiled: February 6, 2023Publication date: August 17, 2023Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
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Publication number: 20230118400Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.Type: ApplicationFiled: October 31, 2022Publication date: April 20, 2023Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
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Patent number: 11572269Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.Type: GrantFiled: November 2, 2020Date of Patent: February 7, 2023Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
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Patent number: 11488934Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.Type: GrantFiled: December 21, 2020Date of Patent: November 1, 2022Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
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Publication number: 20220051973Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.Type: ApplicationFiled: October 14, 2021Publication date: February 17, 2022Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
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Patent number: 11152296Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.Type: GrantFiled: July 23, 2018Date of Patent: October 19, 2021Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD.Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
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Publication number: 20210217725Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.Type: ApplicationFiled: December 21, 2020Publication date: July 15, 2021Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
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Publication number: 20210047172Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.Type: ApplicationFiled: November 2, 2020Publication date: February 18, 2021Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
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Patent number: 10872879Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.Type: GrantFiled: July 17, 2018Date of Patent: December 22, 2020Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
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Patent number: 10822226Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.Type: GrantFiled: January 23, 2019Date of Patent: November 3, 2020Assignee: AMKOR TECHNOLOGY, INC.Inventors: Yung Woo Lee, Byung Jun Kim, Dong Hyun Bang, EunNaRa Cho, Adrian Arcedera, Jae Ung Lee
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Patent number: 10163867Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.Type: GrantFiled: January 15, 2018Date of Patent: December 25, 2018Assignee: Amkor Technology, Inc.Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
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Publication number: 20180350734Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.Type: ApplicationFiled: July 23, 2018Publication date: December 6, 2018Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
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Patent number: 10144634Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.Type: GrantFiled: November 7, 2017Date of Patent: December 4, 2018Assignee: Amkor Technology, Inc.Inventors: Jae Ung Lee, Byong Jin Kim, Young Seok Kim, Wook Choi, Seung Jae Yoo, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang
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Publication number: 20180323170Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.Type: ApplicationFiled: July 17, 2018Publication date: November 8, 2018Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
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Patent number: 10032705Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.Type: GrantFiled: May 8, 2016Date of Patent: July 24, 2018Assignee: Amkor Technology, Inc.Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
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Publication number: 20180138155Abstract: A semiconductor package and a method of manufacturing a semiconductor package.Type: ApplicationFiled: January 15, 2018Publication date: May 17, 2018Inventors: Jin Seong Kim, Edwin J. Adlam, Ludovico E. Bancod, Gi Jung Kim, Robert Lanzone, Jae Ung Lee, Yung Woo Lee, Mi Kyeong Choi
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Publication number: 20180134546Abstract: Disclosed is a semiconductor device including a conductive shield layer formed within a cavity of a molding part and a manufacturing method thereof. Various aspects of the present invention, for example and without limitation, includes a semiconductor device including a conductive shield layer formed along the wall of a cavity to of a molding part to improve EMI shielding performance, and a manufacturing method thereof.Type: ApplicationFiled: November 14, 2016Publication date: May 17, 2018Inventors: Ji Hoon Oh, Byong Jin Kim, Jin Young Kim, Young Seok Kim, EunNaRa Cho, Yung Woo Lee, Do Hyun Na