Abstract: A core partition circuit comprises a first decompression circuit, a second decompression circuit, a first switching circuit, an wrapper scanning circuit, a first compression circuit, a second compression circuit and a second switching circuit. The first and second decompression circuits decompress an input signal. The first switching circuit outputs the output signal of the first decompression circuit or the second decompression circuit according to a first control signal. The wrapper scanning circuit receives the output signal of the first decompression circuit or the second decompression circuit to scan the internal or the port of the core partition circuit. The first and second compression circuits respectively compress the internal logic and the port logic of the core partition circuit. The second switching circuit outputs the compressed internal logic or port logic of the core partition circuit according to the first control signal.

Abstract: A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.

Abstract: A circuit, including a TAP circuit, a routing circuit, a first test path and a second test path, is provided. A first input terminal and a first output terminal of the routing circuit are respectively coupled to a scan output terminal and a first scan input terminal of the TAP circuit. A first terminal of the first test path is coupled to a second input terminal of the routing circuit. A second terminal of the first test path is coupled to a second output terminal of the routing circuit. A first terminal of the second test path is coupled to a third input terminal of the routing circuit. A second terminal of the second test path is coupled to a third output terminal of the routing circuit. The routing circuit couples the scan output terminal of the TAP circuit to the first scan input terminal of the TAP circuit or the first terminal of the first test path or the first terminal of the second test path.

Abstract: A core partition circuit comprises a first decompression circuit, a second decompression circuit, a first switching circuit, an wrapper scanning circuit, a first compression circuit, a second compression circuit and a second switching circuit. The first and second decompression circuits decompress an input signal. The first switching circuit outputs the output signal of the first decompression circuit or the second decompression circuit according to a first control signal. The wrapper scanning circuit receives the output signal of the first decompression circuit or the second decompression circuit to scan the internal or the port of the core partition circuit. The first and second compression circuits respectively compress the internal logic and the port logic of the core partition circuit. The second switching circuit outputs the compressed internal logic or port logic of the core partition circuit according to the first control signal.