Abstract: Provided are an image processing device configured to correct fine fixed pattern noise (FPN), an image processing system, and an operating method thereof. Provided is an operating method of an image processing device, the method including receiving at least one image group including a plurality of images, detecting, from the at least one image group, fixed pattern noise (FPN) information using Fast Fourier Transform (FFT), and correcting FPN based on the FPN information.

Abstract: An image sensor including a substrate having a pixel region, a floating diffusion region in the pixel region of the substrate, a plurality of photoelectric conversion regions around the floating diffusion region in the substrate, a plurality of transmission gates adjacent to the plurality of photoelectric conversion regions, respectively, each including a first buried gate extending to the inside of the substrate, a second buried gate apart from the first buried gate and extending to the inside of the substrate, and a gate connection between the first buried gate and the second buried gate, and a plurality of spacers each on at least parts of side walls of each of the plurality of transmission gates, wherein each of the plurality of spacers is between the side walls of each of the plurality of transmission gates and the floating diffusion region in a plan view.

Abstract: An image sensor includes: a pixel array including a plurality of pixels; and a logic circuit acquiring a pixel signal from the plurality of pixels, wherein each of the plurality of pixels includes a photodiode and a pixel circuit region disposed on the photodiode, wherein the pixel array includes a plurality of pixel groups each having four or more pixels, among the plurality of pixels, adjacent to each other in the first direction and the second direction, wherein the pixel circuit region in each of the plurality of pixel groups includes a plurality of transistors, wherein at least one of the plurality of transistors is a driving transistor including a first active region, a second active region, and a gate structure disposed between the first active region and the second active region in a third direction intersecting the first direction and the second direction.