Abstract: Aspects for vector comparison in neural network are described herein. The aspects may include a direct memory access unit configured to receive a first vector and a second vector from a storage device. The first vector may include one or more first elements and the second vector may include one or more second elements. The aspects may further include a computation module that includes one or more comparers respectively configured to generate a comparison result by comparing one of the one or more first elements to a corresponding one of the one or more second elements in accordance with an instruction.

Abstract: Aspects of processing data for Long Short-Term Memory (LSTM) neural networks are described herein. The aspects may include one or more data buffer units configured to store previous output data at a previous timepoint, input data at a current timepoint, one or more weight values, and one more bias values. The aspects may further include multiple data processing units configured to parallelly calculate a portion of an output value at the current timepoint based on the previous output data at the previous timepoint, the input data at the current timepoint, the one or more weight values, and the one or more bias values.

Abstract: A computing device and related products are provided. The computing device is configured to perform machine learning calculations. The computing device includes an operation unit, a controller unit, and a storage unit. The storage unit includes a data input/output (I/O) unit, a register, and a cache. Technical solution provided by the present disclosure has advantages of fast calculation speed and energy saving.

Abstract: Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector. The first vector may include one or more first elements and the second vector may include one or more second elements. The aspects may further include a computation module configured to calculate a cross product between the first vector and the second vector in response to an instruction.

Abstract: Aspects of data compression/decompression for neural networks are described herein. The aspects may include a model data converter configured to convert neural network content values into pseudo video data. The neural network content values may refer to weight values and bias values of the neural network. The pseudo video data may include one or more pseudo frames. The aspects may further include a compression module configured to encode the pseudo video data into one or more neural network data packages.

Abstract: A communication structure comprises: a central node that is a communication data center of a network-on-chip and used for broadcasting or multicasting communication data to a plurality of leaf nodes; a plurality of leaf nodes that are communication data nodes of the network-on-chip and used for transmitting the communication data to the central node; and forwarder modules for connecting the central node with the plurality of leaf nodes and forwarding the communication data, wherein the plurality of leaf nodes are divided into N groups, each group having the same number of leaf nodes, the central node is individually in communication connection with each group of leaf nodes by means of the forwarder modules, the communication structure is a fractal-tree structure, the communication structure constituted by each group of leaf nodes has self-similarity, and the forwarder modules comprises a central forwarder module, leaf forwarder modules, and intermediate forwarder modules.

Abstract: A computing device and related products are provided. The computing device is configured to perform machine learning calculations. The computing device includes an operation unit, a controller unit, and a storage unit. The storage unit includes a data input/output (I/O) unit, a register, and a cache. Technical solution provided by the present disclosure has advantages of fast calculation speed and energy saving.

Abstract: Aspects for vector circular shifting in neural network are described herein. The aspects may include a direct memory access unit configured to receive a vector that includes multiple elements. The multiple elements are stored in a one-dimensional data structure. The direct memory access unit may store the vector in a vector caching unit. The aspects may further include an instruction caching unit configured to receive a vector shifting instruction that includes a step length for shifting the elements in the vector. Further still, the aspects may include a computation module configured to shift the elements of the vector toward one direction by the step length.

Abstract: An example device comprises a central node for receiving vector data returned by leaf nodes, a plurality of leaf nodes for calculating and shifting the vector data, and forwarder modules comprising a local cache structure and a data processing component, wherein the plurality of leaf nodes are divided into N groups, each group having the same number of leaf nodes; the central node is individually in communication connection with each group of leaf nodes by means of the forwarder modules; a communication structure constituted by each group of leaf nodes has self-similarity; the plurality of leaf nodes are in communication connection with the central node in a complete M-way tree approach by means of the forwarder modules of multiple levels; each of the leaf nodes comprises a setting bit.

Abstract: A compression coding apparatus for artificial neural network, including memory interface unit, instruction cache, controller unit and computing unit, wherein the computing unit is configured to perform corresponding operation to data from the memory interface unit according to instructions of controller unit; the computing unit mainly performs three steps operation: step one is to multiply input neuron by weight data; step two is to perform adder tree computing and add the weighted output neuron obtained in step one level-by-level via adder tree, or add bias to output neuron to get biased output neuron; step three is to perform activation function operation to get final output neuron. The present disclosure also provides a method for compression coding of multi-layer neural network.

Abstract: An apparatus for executing backpropagation of an artificial neural network comprises an instruction caching unit, a controller unit, a direct memory access unit, an interconnection unit, a master computation module, and multiple slave computation modules. For each layer in a multilayer neural network, weighted summation may be performed on input gradient vectors to calculate an output gradient vector of this layer. The output gradient vector may be multiplied by a derivative value of a next-layer activation function on which forward operation is performed, so that a next-layer input gradient vector can be obtained. The input gradient vector may be multiplied by an input neuron counterpoint in forward operation to obtain the gradient of a weight value of this layer, and the weight value of this layer can be updated according to the gradient of the obtained weight value of this layer.

Abstract: An apparatus for executing backpropagation of an artificial neural network comprises an instruction caching unit, a controller unit, a direct memory access unit, an interconnection unit, a master computation module, and multiple slave computation modules. For each layer in a multilayer neural network, weighted summation may be performed on input gradient vectors to calculate an output gradient vector of this layer. The output gradient vector may be multiplied by a derivative value of a next-layer activation function on which forward operation is performed, so that a next-layer input gradient vector can be obtained. The input gradient vector may be multiplied by an input neuron counterpoint in forward operation to obtain the gradient of a weight value of this layer, and the weight value of this layer can be updated according to the gradient of the obtained weight value of this layer.

Abstract: A method may include: partitioning data on an on-chip and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block; and a data indexing step for successively loading different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing. Data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block, and the data partitioned into the same data block can be loaded on a chip once for storage, and is then used as many times as possible, so that the access is more efficient.

Abstract: Aspects for backpropagation of a convolutional neural network are described herein. The aspects may include a direct memory access unit configured to receive input data from a storage device and a master computation module configured to select one or more portions of the input data based on a predetermined convolution window. Further, the aspects may include one or more slave computation modules respectively configured to convolute one of the one or more portions of the input data with one of one or more previously calculated first data gradients to generate a kernel gradient, wherein the master computation module is further configured to update a prestored convolution kernel based on the kernel gradient.

Abstract: Aspects of a neural network convolution device are described herein. The aspects may include a matrix transformer and a matrix multiplication module. The matrix transformer may be configured to receive an input data matrix and a weight matrix, transform the input data matrix into a transformed input data matrix based on a first transformation matrix, and transform the weight matrix into a transformed weight matrix based on a second transformation matrix. The matrix multiplication module may be configured to multiply one or more input data elements in the transformed input data matrix with one or more weight elements in the transformed weight matrix to generate an intermediate output matrix. The matrix transformer may be further configured to transform the intermediate output matrix into an output matrix based on an inverse transformation matrix.

Abstract: Aspects for forward propagation of a convolutional artificial neural network are described herein. The aspects may include a direct memory access unit configured to receive input data from a storage device and a master computation module configured to select one or more portions of the input data based on a predetermined convolution window. Further, the aspects may include one or more slave computation modules respectively configured to convolute a convolution kernel with one of the one or more portions of the input data to generate a slave output value. Further still, the aspects may include an interconnection unit configured to combine the one or more slave output values into one or more intermediate result vectors, wherein the master computation module is further configured to merge the one or more intermediate result vectors into a merged intermediate vector.

Abstract: Aspects for backpropagation of a convolutional neural network are described herein. The aspects may include a direct memory access unit configured to receive input data from a storage device and a master computation module configured to select one or more portions of the input data based on a predetermined convolution window. Further, the aspects may include one or more slave computation modules respectively configured to convolute one of the one or more portions of the input data with one of one or more previously calculated first data gradients to generate a kernel gradient, wherein the master computation module is further configured to update a prestored convolution kernel based on the kernel gradient.

Abstract: Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector. The first vector may include one or more first elements and the second vector may include one or more second elements. The aspects may further include a computation module configured to calculate a cross product between the first vector and the second vector in response to an instruction.

Abstract: Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include one or more adders and a combiner. The one or more adders may be configured to respectively add each of the first elements to a corresponding one of the second elements to generate one or more addition results. The combiner may be configured to combine a combiner configured to combine the one or more addition results into an output vector.

Abstract: Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include one or more adders and a combiner. The one or more adders may be configured to respectively add each of the first elements to a corresponding one of the second elements to generate one or more addition results. The combiner may be configured to combine a combiner configured to combine the one or more addition results into an output vector.