Patents by Inventor Yunjun Ho
Yunjun Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10784144Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.Type: GrantFiled: February 15, 2018Date of Patent: September 22, 2020Assignee: Intel CorporationInventors: James Mathew, Yunjun Ho, Zhiqiang Xie, Hyun Sik Kim
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Publication number: 20180174890Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: James Mathew, Yunjun Ho, Zhiqiang Xie, Hyun Sik Kim
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Patent number: 9935000Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.Type: GrantFiled: February 29, 2016Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: James Mathew, Yunjun Ho, Zhiqiang Xie, Hyun Sik Kim
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Publication number: 20170250108Abstract: A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.Type: ApplicationFiled: February 29, 2016Publication date: August 31, 2017Inventors: James Mathew, Yunjun Ho, Zhiqiang Xie, Hyun Sik Kim
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Patent number: 8575716Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.Type: GrantFiled: May 14, 2013Date of Patent: November 5, 2013Assignee: Micron Technology, Inc.Inventors: James Mathew, Brett D. Lowe, Yunjun Ho, H. Jim Fulford, Jie Sun, Zhaoli Sun
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Publication number: 20130249050Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.Type: ApplicationFiled: May 14, 2013Publication date: September 26, 2013Applicant: Micron Technology, Inc.Inventors: James Mathew, Brett D. Lowe, Yunjun Ho, H. Jim Fulford, Jie Sun, Zhaoli Sun
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Patent number: 8461016Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.Type: GrantFiled: October 7, 2011Date of Patent: June 11, 2013Assignee: Micron Technology, Inc.Inventors: James Mathew, Brett D. Lowe, Yunjun Ho, H. Jim Fulford, Jie Sun, Zhaoli Sun
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Patent number: 8450218Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.Type: GrantFiled: December 28, 2011Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Yunjun Ho, Brent Gilgen
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Publication number: 20130087883Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.Type: ApplicationFiled: October 7, 2011Publication date: April 11, 2013Inventors: James Mathew, Brett D. Lowe, Yunjun Ho, H. Jim Fulford, Jie Sun, Zhaoli Sun
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Publication number: 20120100726Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.Type: ApplicationFiled: December 28, 2011Publication date: April 26, 2012Inventors: Yunjun Ho, Brent Gilgen
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Patent number: 8105956Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.Type: GrantFiled: October 20, 2009Date of Patent: January 31, 2012Assignee: Micron Technology, Inc.Inventors: Yunjun Ho, Brent Gilgen
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Patent number: 8030170Abstract: Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500° C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700° C. to about 1000° C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another.Type: GrantFiled: December 8, 2009Date of Patent: October 4, 2011Assignee: Micron Technology, Inc.Inventors: Yunjun Ho, Matt Meyers, Kevin L. Beaman, Gregory J. Light
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Publication number: 20110136319Abstract: Some embodiments include methods of forming isolation structures. A trench may be formed to extend into a semiconductor material. Polysilazane may be formed within the trench, and then exposed to steam. A maximum temperature of the polysilazane during the steam exposure may be less than or equal to about 500° C. The steam exposure may convert all of the polysilazane to silicon oxide. The silicon oxide may be annealed under an inert atmosphere. A maximum temperature of the silicon oxide during the annealing may be from about 700° C. to about 1000° C. In some embodiments, the isolation structures are utilized to isolate nonvolatile memory components from one another.Type: ApplicationFiled: December 8, 2009Publication date: June 9, 2011Inventors: Yunjun Ho, Matt Meyers, Kevin L. Beaman, Gregory J. Light
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Publication number: 20110092061Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.Type: ApplicationFiled: October 20, 2009Publication date: April 21, 2011Inventors: Yunjun Ho, Brent Gilgen