Patents by Inventor Yunkun WANG

Yunkun WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10530258
    Abstract: A predictive dead time generating circuit includes a dead time detecting module configured to detect a dead time between the switching off of the upper power transistor and the switching on of the lower power transistor, and a dead time between the switching off of the lower power transistor and the switching on of the upper power transistor, and to generate a first detecting signal and a second detecting signal according to the condition of whether the detected dead time reaches an optimal value. The logic control module changes the output of the delay module according to the judgment result of the dead time detecting module, so as to change the dead time between the driving signal of the upper power transistor and the driving signal of the lower power transistor.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: January 7, 2020
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Zekun Zhou, Yunkun Wang, Yandong Yuan, Shilei Li, Zhuo Wang, Bo Zhang
  • Patent number: 10146238
    Abstract: A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to ?T2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of ?40° C.˜100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from ?W level to nW level and realize low power consumption.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 4, 2018
    Assignee: University of Electronic Science and Technology of China
    Inventors: Zekun Zhou, Yao Wang, Jianwen Cao, Hongming Yu, Yunkun Wang, Anqi Wang, Zhuo Wang, Bo Zhang
  • Publication number: 20180164842
    Abstract: A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to ?T2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of ?40° C.˜ 100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from ?W level to nW level and realize low power consumption.
    Type: Application
    Filed: May 19, 2017
    Publication date: June 14, 2018
    Applicant: University of Electronic Science and Technology of China
    Inventors: Zekun ZHOU, Yao WANG, Jianwen CAO, Hongming YU, Yunkun WANG, Anqi WANG, Zhuo WANG, Bo ZHANG