Patents by Inventor Yunlei QI
Yunlei QI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876884Abstract: This application provides a communication method and an optical module. The method includes: A first optical module determines a first delay. The first optical module sends the first delay to an interface chip. According to the communication method and the optical module that are provided in this application, a delay in the optical module can be reported to the interface chip, so as to improve precision of time synchronization between a master clock and a slave clock, thereby further improving clock precision of a network device.Type: GrantFiled: July 7, 2021Date of Patent: January 16, 2024Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yunlei Qi, Chunrong Li
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Patent number: 11843452Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.Type: GrantFiled: December 27, 2022Date of Patent: December 12, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xiang He, Yunlei Qi, Jingfeng Chen, Tao Lin, Junmin Song, Xinyuan Wang
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Publication number: 20230388984Abstract: A communication method and device, and a chip system adjust, by adjusting a quantity of slot resources included in a multiframe, a bandwidth resource corresponding to one multiframe. A first communication device sends a first request message. The first request message is used to request to adjust a quantity of basic frames in a multiframe included in a first block sequence. The first communication device multiplexes, based on S1 slot resources corresponding to the adjusted multiframe in the first block sequence, Q1 first block sequences corresponding to a slot resource in the S1 slot resources, to obtain and send the first block sequence.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Li Xu, Qiwen Zhong, Jingfeng Chen, Yunlei Qi
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Patent number: 11824636Abstract: This disclosure provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.Type: GrantFiled: June 6, 2022Date of Patent: November 21, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xiang He, Yunlei Qi, Jingfeng Chen, Tao Lin, Junmin Song, Xinyuan Wang
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Publication number: 20230155756Abstract: This application provides a data transmission method, a communications apparatus, a network device, a communications system, a storage medium, and a computer program product, to resolve a current problem that bandwidth waste is relatively severe when a service is carried based on a FlexE technology. In this application, a frame structure of a fine-granularity service frame is newly defined, so that service data can be transmitted in a time division multiplexing mode by using an Ethernet (ETH) interface.Type: ApplicationFiled: January 18, 2023Publication date: May 18, 2023Inventors: Yunlei Qi, Qiwen Zhong, Zhigang Zhu, Kai Liu, Jingfeng Chen
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Publication number: 20230138058Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.Type: ApplicationFiled: December 27, 2022Publication date: May 4, 2023Inventors: Xiang He, Yunlei Qi, Jingfeng Chen, Tao Lin, Junmin Song, Xinyuan Wang
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Patent number: 11641266Abstract: A device determines a first latency value of a first data flow from a first physical port of the device to a second physical port of the device and a second latency value of a second data flow from the second physical port to the first physical port, where the first latency value is less than the second latency value. The device determines a first target latency value based on the first latency value and the second latency value. The device adjusts a latency value of the first data flow to the first target latency value.Type: GrantFiled: September 11, 2020Date of Patent: May 2, 2023Assignee: Huawei Technologies Co., Ltd.Inventors: Yunlei Qi, Chunrong Li
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Patent number: 11588568Abstract: A packet processing method includes receiving a first packet by a first receiving interface of a media conversion module of a first network device, where the first packet includes a first alignment marker (AM), sending a second packet by a first sending interface of the media conversion module, where the second packet includes the first AM, and where the second packet is the first packet processed by the media conversion module, and calculating a time interval T1 between a time at which the media conversion module receives the first packet and a time at which the media conversion module sends the second packet, where the T1 is used to compensate for a first timestamp at which the first network device receives or sends the third packet.Type: GrantFiled: January 14, 2022Date of Patent: February 21, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Jinhui Wang, Liqing Chen, Hongwei Niu, Yunlei Qi
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Patent number: 11552721Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.Type: GrantFiled: August 16, 2021Date of Patent: January 10, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xiang He, Yunlei Qi, Jingfeng Chen, Tao Lin, Junmin Song, Xinyuan Wang
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Publication number: 20220303035Abstract: This disclosure provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.Type: ApplicationFiled: June 6, 2022Publication date: September 22, 2022Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xiang He, Yunlei Qi, Jingfeng Chen, Tao Lin, Junmin Song, Xinyuan Wang
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Patent number: 11356188Abstract: This application provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.Type: GrantFiled: April 13, 2020Date of Patent: June 7, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xiang He, Yunlei Qi, Jingfeng Chen, Tao Lin, Junmin Song, Xinyuan Wang
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Patent number: 11343007Abstract: A time synchronization method includes receiving, by a receive-end device, a first timestamp and a first header signal sent by a transmit-end device, where the first timestamp indicates a first moment at which a first channel medium conversion module sends the first header signal, and a second moment at which the receive-end device receives the first header signal. The method further includes sending a second header signal to the transmit-end device, where a third moment at which the receive-end device sends the second header signal. The method further includes receiving a fourth timestamp sent by the transmit-end device, where the fourth timestamp indicates a fourth moment at which the transmit-end device receives the second header signal. The method further includes synchronizing time with the transmit-end device based on the first moment, the second moment, the third moment, and the fourth moment.Type: GrantFiled: December 30, 2019Date of Patent: May 24, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Jinhui Wang, Song Liu, Hongwei Niu, Yunlei Qi
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Publication number: 20220140929Abstract: A packet processing method includes receiving a first packet by a first receiving interface of a media conversion module of a first network device, where the first packet includes a first alignment marker (AM), sending a second packet by a first sending interface of the media conversion module, where the second packet includes the first AM, and where the second packet is the first packet processed by the media conversion module, and calculating a time interval T1 between a time at which the media conversion module receives the first packet and a time at which the media conversion module sends the second packet, where the T1 is used to compensate for a first timestamp at which the first network device receives or sends the third packet.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Inventors: Jinhui Wang, Liqing Chen, Hongwei Niu, Yunlei Qi
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Patent number: 11245483Abstract: A packet processing method includes receiving a first packet by a first receiving interface of a media conversion module of a first network device, where the first packet includes a first alignment marker (AM), sending a second packet by a first sending interface of the media conversion module, where the second packet includes the first AM, and the second packet is the first packet processed by the media conversion module, and calculating a time interval T1 between a time at which the media conversion module receives the first packet and a time at which the media conversion module sends the second packet, where the T1 is used to compensate for a first timestamp at which the first network device receives or sends the third packet.Type: GrantFiled: February 21, 2020Date of Patent: February 8, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Jinhui Wang, Liqing Chen, Hongwei Niu, Yunlei Qi
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Patent number: 11218572Abstract: A packet processing method includes: obtaining, at a Medium Access Control (MAC) layer, a first fragmented data frame included in a first data frame; buffering the first fragmented data frame into a first queue; obtaining, at the MAC layer, a second fragmented data frame included in a second data frame; buffering the second fragmented data frame into a second queue; sending the first fragmented data frame to a forwarding processing module; obtaining first forwarding information using the forwarding processing module; sending the second fragmented data frame to the forwarding processing module after sending the first fragmented data frame to the forwarding processing module; and obtaining second forwarding information.Type: GrantFiled: August 13, 2019Date of Patent: January 4, 2022Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yunlei Qi, Chunrong Li, Yongjian Hu
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Publication number: 20210376943Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.Type: ApplicationFiled: August 16, 2021Publication date: December 2, 2021Inventors: Xiang He, Yunlei Qi, Jingfeng Chen, Tao Lin, Junmin Song, Xinyuan Wang
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Publication number: 20210336762Abstract: This application provides a communication method and an optical module. The method includes: A first optical module determines a first delay. The first optical module sends the first delay to an interface chip. According to the communication method and the optical module that are provided in this application, a delay in the optical module can be reported to the interface chip, so as to improve precision of time synchronization between a master clock and a slave clock, thereby further improving clock precision of a network device.Type: ApplicationFiled: July 7, 2021Publication date: October 28, 2021Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yunlei Qi, Chunrong Li
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Patent number: 11108485Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.Type: GrantFiled: April 28, 2020Date of Patent: August 31, 2021Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Xiang He, Yunlei Qi, Jingfeng Chen, Tao Lin, Junmin Song, Xinyuan Wang
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Publication number: 20210006386Abstract: A device determines a first latency value of a first data flow from a first physical port of the device to a second physical port of the device and a second latency value of a second data flow from the second physical port to the first physical port, where the first latency value is less than the second latency value. The device determines a first target latency value based on the first latency value and the second latency value. The device adjusts a latency value of the first data flow to the first target latency value.Type: ApplicationFiled: September 11, 2020Publication date: January 7, 2021Inventors: Yunlei Qi, Chunrong Li
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Publication number: 20200259578Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Xiang He, Yunlei Qi, Jingfeng Chen, Tao Lin, Junmin Song, Xinyuan Wang